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[/] [ft816float/] [trunk/] [rtl/] [positVerilog/] [positCntlz.sv] - Diff between revs 36 and 42

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`include "positConfig.sv"
`include "positConfig.sv"
// ============================================================================
// ============================================================================
//        __
//        __
//   \\__/ o\    (C) 2020  Robert Finch, Waterloo
//   \\__/ o\    (C) 2020  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//    \  __ /    All rights reserved.
//     \/_//     robfinch@finitron.ca
//     \/_//     robfinch@finitron.ca
//       ||
//       ||
//
//
//      positCntlz.sv
//      positCntlz.sv
//
//
// This source file is free software: you can redistribute it and/or modify
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
// (at your option) any later version.
//
//
// This source file is distributed in the hope that it will be useful,
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
// GNU General Public License for more details.
//
//
// You should have received a copy of the GNU General Public License
// You should have received a copy of the GNU General Public License
// along with this program.  If not, see .
// along with this program.  If not, see .
//
//
// ============================================================================
// ============================================================================
//
//
module positCntlz(i, o);
module positCntlz(i, o);
parameter PSTWID = `PSTWID;
parameter PSTWID = `PSTWID;
input [PSTWID-2:0] i;
input [PSTWID-2:0] i;
output [$clog2(PSTWID-2):0] o;
output [$clog2(PSTWID-1)-1:0] o;
 
 
generate begin : gClz
generate begin : gClz
  case(PSTWID)
  if (PSTWID <= 8)
  16: cntlz16 u1 (.i({i,1'b1}), .o(o));
    cntlz8 u1 (.i({i,{9-PSTWID{1'b1}}}), .o(o));
  20: cntlz24 u1 (.i({i,1'b1,4'hF}), .o(o));
  else if (PSTWID <= 16)
  32: cntlz32 u1 (.i({i,1'b1}), .o(o));
    cntlz16 u1 (.i({i,{17-PSTWID{1'b1}}}), .o(o));
  40: cntlz48 u1 (.i({i,1'b1,8'hFF}), .o(o));
  else if (PSTWID <= 24)
  52: cntlz64 u1 (.i({i,1'b1,12'hFFF}), .o(o));
    cntlz24 u1 (.i({i,{25-PSTWID{1'b1}}}), .o(o));
  64: cntlz64 u1 (.i({i,1'b1}), .o(o));
  else if (PSTWID <= 32)
  80: cntlz80 u1 (.i({i,1'b1}), .o(o));
    cntlz32 u1 (.i({i,{33-PSTWID{1'b1}}}), .o(o));
  default:  ;
  else if (PSTWID <= 48)
  endcase
    cntlz48 u1 (.i({i,{49-PSTWID{1'b1}}}), .o(o));
 
  else if (PSTWID <= 64)
 
    cntlz64 u1 (.i({i,{65-PSTWID{1'b1}}}), .o(o));
 
  else if (PSTWID <= 80)
 
    cntlz80 u1 (.i({i,{81-PSTWID{1'b1}}}), .o(o));
 
  else if (PSTWID <= 96)
 
    cntlz96 u1 (.i({i,{97-PSTWID{1'b1}}}), .o(o));
 
  else if (PSTWID <= 128)
 
    cntlz128 u1 (.i({i,{129-PSTWID{1'b1}}}), .o(o));
end
end
endgenerate
endgenerate
endmodule
endmodule
 
 

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