// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2020 Robert Finch, Waterloo
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// \\__/ o\ (C) 2020 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// \/_// robfinch@finitron.ca
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// ||
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// ||
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//
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//
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// positFDPMul.v
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// positFDPMul.sv
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// - fused dot product posit number multiplier
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// - fused dot product posit number multiplier
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// - parameterized width
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// - parameterized width
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// - perform a multiplication but retain all the product bits
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// - perform a multiplication but retain all the product bits
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// in the result in preparation for addition.
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// in the result in preparation for addition.
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//
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see .
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// along with this program. If not, see .
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//
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//
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// ============================================================================
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// ============================================================================
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`include "positConfig.sv"
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import posit::*;
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module positFDPMul(a, b, o, zero, inf);
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module positFDPMul(a, b, o, zero, inf);
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`include "positSize.sv"
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localparam rs = $clog2(PSTWID-1);
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input [PSTWID-1:0] a;
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input [PSTWID-1:0] a;
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input [PSTWID-1:0] b;
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input [PSTWID-1:0] b;
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output reg [PSTWID+es+(PSTWID-es)*2-1:0] o;
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output reg [PSTWID+es+(PSTWID-es)*2-1:0] o;
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output zero;
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output zero;
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output inf;
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output inf;
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wire sa, sb, so;
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wire sa, sb, so;
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wire [rs:0] rgma, rgmb;
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wire [rs:0] rgma, rgmb;
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wire [rs+1:0] rgm1, rgm2;
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wire [rs+1:0] rgm1, rgm2;
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wire rgsa, rgsb;
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wire rgsa, rgsb;
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wire [es-1:0] expa, expb;
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wire [es-1:0] expa, expb;
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wire [PSTWID-es-1:0] siga, sigb;
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wire [PSTWID-es-1:0] siga, sigb;
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wire [(PSTWID-es)*2-1:0] prod;
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wire [(PSTWID-es)*2-1:0] prod;
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wire zera, zerb;
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wire zera, zerb;
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wire infa, infb;
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wire infa, infb;
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wire inf = infa|infb;
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wire inf = infa|infb;
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wire zero = zera|zerb;
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wire zero = zera|zerb;
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positDecompose #(PSTWID,es) u1 (
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positDecompose #(PSTWID) u1 (
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.i(a),
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.i(a),
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.sgn(sa),
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.sgn(sa),
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.rgs(rgsa),
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.rgs(rgsa),
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.rgm(rgma),
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.rgm(rgma),
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.exp(expa),
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.exp(expa),
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.sig(siga),
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.sig(siga),
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.zer(zera),
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.zer(zera),
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.inf(infa)
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.inf(infa)
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);
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);
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positDecompose #(PSTWID,es) u2 (
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positDecompose #(PSTWID) u2 (
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.i(b),
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.i(b),
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.sgn(sb),
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.sgn(sb),
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.rgs(rgsb),
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.rgs(rgsb),
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.rgm(rgmb),
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.rgm(rgmb),
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.exp(expb),
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.exp(expb),
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.sig(sigb),
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.sig(sigb),
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.zer(zerb),
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.zer(zerb),
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.inf(infb)
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.inf(infb)
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);
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);
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assign so = sa ^ sb; // compute sign
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assign so = sa ^ sb; // compute sign
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assign prod = siga * sigb;
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assign prod = siga * sigb;
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// The product could have one or two whole digits before the point. Detect which it is
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// The product could have one or two whole digits before the point. Detect which it is
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// and realign the product.
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// and realign the product.
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wire mo = prod[(PSTWID-es)*2-1];
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wire mo = prod[(PSTWID-es)*2-1];
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wire [(PSTWID-es)*2-1:0] prod1 = mo ? prod : prod << 1'b1; // left align product
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wire [(PSTWID-es)*2-1:0] prod1 = mo ? prod : prod << 1'b1; // left align product
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// Convert to the real +/- regime value
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// Convert to the real +/- regime value
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assign rgm1 = rgsa ? rgma : -rgma;
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assign rgm1 = rgsa ? rgma : -rgma;
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assign rgm2 = rgsb ? rgmb : -rgmb;
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assign rgm2 = rgsb ? rgmb : -rgmb;
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// Compute regime and exponent, include product alignment shift.
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// Compute regime and exponent, include product alignment shift.
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wire [rs+es+1:0] rxtmp = {rgm1,expa} + {rgm2,expb} + mo;
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wire [rs+es+1:0] rxtmp = {rgm1,expa} + {rgm2,expb} + mo;
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// Make a negative rx positive
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// Make a negative rx positive
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wire [rs+es+1:0] rxtmp2c = rxtmp[rs+es+1] ? ~rxtmp + 2'd1 : rxtmp;
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wire [rs+es+1:0] rxtmp2c = rxtmp[rs+es+1] ? ~rxtmp + 2'd1 : rxtmp;
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// Break out the exponent and regime portions
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// Break out the exponent and regime portions
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wire [es-1:0] exp = |es ? rxtmp[es-1:0] : 0;
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wire [es-1:0] exp = |es ? rxtmp[es-1:0] : 0;
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// Take absolute value of regime portion
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// Take absolute value of regime portion
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wire srxtmp = rxtmp[rs+es+1];
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wire srxtmp = rxtmp[rs+es+1];
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wire [rs:0] rgm = srxtmp ? -rxtmp[rs+es+1:es] : rxtmp[rs+es+1:es];
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wire [rs:0] rgm = srxtmp ? -rxtmp[rs+es+1:es] : rxtmp[rs+es+1:es];
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// Compute the length of the regime bit string, +1 for positive regime
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// Compute the length of the regime bit string, +1 for positive regime
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wire [rs+es+1:0] rxn = rxtmp[rs+es+1] ? rxtmp2c : rxtmp;
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wire [rs+es+1:0] rxn = rxtmp[rs+es+1] ? rxtmp2c : rxtmp;
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wire [rs:0] rgml;
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wire [rs:0] rgml;
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// Build expanded posit number:
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// Build expanded posit number:
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// trim one leading bit off the product bits
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// trim one leading bit off the product bits
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// and keep guard, round bits, and create sticky bit
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// and keep guard, round bits, and create sticky bit
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wire [PSTWID+es+(PSTWID-es)*2-2:0] tmp;
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wire [PSTWID+es+(PSTWID-es)*2-2:0] tmp;
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generate begin : gTmp
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generate begin : gTmp
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if (es > 0) begin
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if (es > 0) begin
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assign rgml = (~srxtmp | |(rxn[es-1:0])) ? rxtmp2c[rs+es:es] + 2'd1 : rxtmp2c[rs+es:es];
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assign rgml = (~srxtmp | |(rxn[es-1:0])) ? rxtmp2c[rs+es:es] + 2'd1 : rxtmp2c[rs+es:es];
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assign tmp = {{PSTWID-1{~srxtmp}},srxtmp,exp,prod1[(PSTWID-es)*2-2:0]};
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assign tmp = {{PSTWID-1{~srxtmp}},srxtmp,exp,prod1[(PSTWID-es)*2-2:0]};
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end
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end
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else begin
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else begin
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assign rgml = (~srxtmp) ? rxtmp2c[rs+es:es] + 2'd1 : rxtmp2c[rs+es:es];
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assign rgml = (~srxtmp) ? rxtmp2c[rs+es:es] + 2'd1 : rxtmp2c[rs+es:es];
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assign tmp = {{PSTWID-1{~srxtmp}},srxtmp,prod1[(PSTWID-es)*2-2:0]};
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assign tmp = {{PSTWID-1{~srxtmp}},srxtmp,prod1[(PSTWID-es)*2-2:0]};
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end
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end
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end
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end
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endgenerate
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endgenerate
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wire [PSTWID+es+(PSTWID-es)*2-2:0] tmp1 = tmp << (PSTWID-rgml-1);
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wire [PSTWID+es+(PSTWID-es)*2-2:0] tmp1 = tmp << (PSTWID-rgml-1);
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wire [PSTWID+es+(PSTWID-es)*2-1:0] abstmp = so ? {1'b1,-tmp1} : {1'b0,tmp1};
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wire [PSTWID+es+(PSTWID-es)*2-1:0] abstmp = so ? {1'b1,-tmp1} : {1'b0,tmp1};
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always @*
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always @*
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casez({zero,inf})
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casez({zero,inf})
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2'b1?: o = {PSTWID+es+(PSTWID-es)*2-2{1'b0}};
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2'b1?: o = {PSTWID+es+(PSTWID-es)*2-2{1'b0}};
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2'b01: o = {1'b1,{PSTWID+es+(PSTWID-es)*2-2-1{1'b0}}};
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2'b01: o = {1'b1,{PSTWID+es+(PSTWID-es)*2-2-1{1'b0}}};
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default: o = abstmp;
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default: o = abstmp;
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endcase
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endcase
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endmodule
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endmodule
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