// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2006-2020 Robert Finch, Waterloo
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// \\__/ o\ (C) 2006-2020 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// \/_// robfinch@finitron.ca
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// ||
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// ||
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//
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//
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// DFPNormalize.sv
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// DFPNormalize.sv
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// - decimal floating point normalization unit
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// - decimal floating point normalization unit
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// - eight cycle latency
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// - eight cycle latency
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// - parameterized width
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// - parameterized width
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//
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see .
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// along with this program. If not, see .
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//
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//
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// This unit takes a floating point number in an intermediate
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// This unit takes a floating point number in an intermediate
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// format and normalizes it. No normalization occurs
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// format and normalizes it. No normalization occurs
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// for NaN's or infinities. The unit has a two cycle latency.
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// for NaN's or infinities. The unit has a two cycle latency.
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//
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//
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// The mantissa is assumed to start with two whole bits on
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// The mantissa is assumed to start with two whole bits on
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// the left. The remaining bits are fractional.
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// the left. The remaining bits are fractional.
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//
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//
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// The width of the incoming format is reduced via a generation
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// The width of the incoming format is reduced via a generation
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// of sticky bit in place of the low order fractional bits.
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// of sticky bit in place of the low order fractional bits.
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//
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//
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// On an underflowed input, the incoming exponent is assumed
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// On an underflowed input, the incoming exponent is assumed
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// to be negative. A right shift is needed.
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// to be negative. A right shift is needed.
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// ============================================================================
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// ============================================================================
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import fp::*;
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import fp::*;
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module DFPNormalize(clk, ce, i, o, under_i, under_o, inexact_o);
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module DFPNormalize(clk, ce, i, o, under_i, under_o, inexact_o);
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parameter N=33;
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parameter N=33;
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input clk;
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input clk;
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input ce;
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input ce;
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input [(N+1)*4*2+16+4-1:0] i; // expanded format input
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input [(N+1)*4*2+16+4-1:0] i; // expanded format input
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output [N*4+16+4-1+4:0] o; // normalized output + guard, sticky and round bits, + 1 whole digit
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output [N*4+16+4-1+4:0] o; // normalized output + guard, sticky and round bits, + 1 whole digit
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input under_i;
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input under_i;
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output under_o;
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output under_o;
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output inexact_o;
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output inexact_o;
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integer n;
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integer n;
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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// No Clock required
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// No Clock required
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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reg [15:0] xo0;
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reg [15:0] xo0;
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reg so0;
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reg so0;
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reg sx0;
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reg sx0;
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reg nan0;
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reg nan0;
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reg inf0;
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reg inf0;
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always @*
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always @*
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xo0 <= i[(N+1)*4*2+15:(N+1)*4*2];
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xo0 <= i[(N+1)*4*2+15:(N+1)*4*2];
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always @*
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always @*
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so0 <= i[(N+1)*4*2+16+4-2]; // sign doesn't change
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so0 <= i[(N+1)*4*2+16+4-2]; // sign doesn't change
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always @*
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always @*
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sx0 <= i[(N+1)*4*2+16+4-4];
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sx0 <= i[(N+1)*4*2+16+4-4];
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always @*
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always @*
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nan0 <= i[(N+1)*4*2+16+4-1];
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nan0 <= i[(N+1)*4*2+16+4-1];
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always @*
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always @*
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inf0 <= i[(N+1)*4*2+16+4-3] || xo0==16'h9999 && i[(N+1)*4*2-4];
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inf0 <= i[(N+1)*4*2+16+4-3] || xo0==16'h9999 && i[(N+1)*4*2-4];
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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// Clock #1
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// Clock #1
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// - Capture exponent information
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// - Capture exponent information
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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reg xInf1a, xInf1b, xInf1c;
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reg xInf1a, xInf1b, xInf1c;
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wire [(N+1)*4*2+16+4-1:0] i1;
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wire [(N+1)*4*2+16+4-1:0] i1;
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delay #(.WID((N+2)*4*2+16+4),.DEP(1)) u11 (.clk(clk), .ce(ce), .i(i), .o(i1));
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delay #(.WID((N+2)*4*2+16+4),.DEP(1)) u11 (.clk(clk), .ce(ce), .i(i), .o(i1));
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always @(posedge clk)
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always @(posedge clk)
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if (ce) xInf1a <= xo0==16'h9999 & !under_i;
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if (ce) xInf1a <= xo0==16'h9999 & !under_i;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) xInf1b <= xo0==16'h9998 & !under_i;
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if (ce) xInf1b <= xo0==16'h9998 & !under_i;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) xInf1c <= xo0==16'h9999;
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if (ce) xInf1c <= xo0==16'h9999;
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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// Clock #2
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// Clock #2
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// - determine exponent increment
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// - determine exponent increment
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// Since the there are *three* whole digits in the incoming format
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// Since the there are *three* whole digits in the incoming format
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// the number of whole digits needs to be reduced. If the MSB is
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// the number of whole digits needs to be reduced. If the MSB is
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// set, then increment the exponent and no shift is needed.
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// set, then increment the exponent and no shift is needed.
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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wire xInf2c, xInf2b;
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wire xInf2c, xInf2b;
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wire [15:0] xo2;
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wire [15:0] xo2;
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reg incExpByOne2, incExpByTwo2;
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reg incExpByOne2, incExpByTwo2;
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delay #(.WID(1),.DEP(1)) u21 (.clk(clk), .ce(ce), .i(xInf1c), .o(xInf2c));
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delay #(.WID(1),.DEP(1)) u21 (.clk(clk), .ce(ce), .i(xInf1c), .o(xInf2c));
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delay #(.WID(1),.DEP(1)) u22 (.clk(clk), .ce(ce), .i(xInf1b), .o(xInf2b));
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delay #(.WID(1),.DEP(1)) u22 (.clk(clk), .ce(ce), .i(xInf1b), .o(xInf2b));
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delay #(.WID(16),.DEP(2)) u23 (.clk(clk), .ce(ce), .i(xo0), .o(xo2));
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delay #(.WID(16),.DEP(2)) u23 (.clk(clk), .ce(ce), .i(xo0), .o(xo2));
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delay #(.WID(1),.DEP(2)) u24 (.clk(clk), .ce(ce), .i(under_i), .o(under2));
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delay #(.WID(1),.DEP(2)) u24 (.clk(clk), .ce(ce), .i(under_i), .o(under2));
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always @(posedge clk)
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always @(posedge clk)
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if (ce) incExpByOne2 <= !xInf1a & i1[(N+1)*4*2-4];
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if (ce) incExpByOne2 <= !xInf1a & i1[(N+1)*4*2-4];
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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// Clock #3
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// Clock #3
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// - increment exponent
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// - increment exponent
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// - detect a zero mantissa
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// - detect a zero mantissa
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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wire incExpByOne3;
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wire incExpByOne3;
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wire [(N+1)*4*2+16+4-1:0] i3;
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wire [(N+1)*4*2+16+4-1:0] i3;
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reg [15:0] xo3;
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reg [15:0] xo3;
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reg zeroMan3;
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reg zeroMan3;
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delay #(.WID(1),.DEP(1)) u32 (.clk(clk), .ce(ce), .i(incExpByOne2), .o(incExpByOne3));
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delay #(.WID(1),.DEP(1)) u32 (.clk(clk), .ce(ce), .i(incExpByOne2), .o(incExpByOne3));
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delay #(.WID((N+1)*4*2+16+4),.DEP(3)) u33 (.clk(clk), .ce(ce), .i(i[(N+3)*4*2+16+4-1:0]), .o(i3));
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delay #(.WID((N+1)*4*2+16+4),.DEP(3)) u33 (.clk(clk), .ce(ce), .i(i[(N+3)*4*2+16+4-1:0]), .o(i3));
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wire [15:0] xo2a;
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wire [15:0] xo2a;
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BCDAddN #(.N(4)) ubcdan1
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BCDAddN #(.N(4)) ubcdan1
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(
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(
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.ci(1'b0),
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.ci(1'b0),
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.a(xo2),
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.a(xo2),
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.b(16'h0001),
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.b(16'h0001),
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.o(xo2a),
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.o(xo2a),
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.co()
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.co()
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);
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);
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always @(posedge clk)
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always @(posedge clk)
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if (ce) xo3 <= (incExpByOne2 ? xo2a : xo2);
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if (ce) xo3 <= (incExpByOne2 ? xo2a : xo2);
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always @(posedge clk)
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always @(posedge clk)
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if(ce) zeroMan3 <= 1'b0;
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if(ce) zeroMan3 <= 1'b0;
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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// Clock #4
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// Clock #4
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// - Shift mantissa left
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// - Shift mantissa left
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// - If infinity is reached then set the mantissa to zero
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// - If infinity is reached then set the mantissa to zero
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// shift mantissa left to reduce to a single whole digit
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// shift mantissa left to reduce to a single whole digit
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// - create sticky bit
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// - create sticky bit
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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reg [(N+2)*4-1:0] mo4;
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reg [(N+2)*4-1:0] mo4;
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reg inexact4;
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reg inexact4;
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always @(posedge clk)
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always @(posedge clk)
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if(ce)
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if(ce)
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casez({zeroMan3,incExpByOne3})
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casez({zeroMan3,incExpByOne3})
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2'b1?: mo4 <= 1'd0;
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2'b1?: mo4 <= 1'd0;
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2'b01: mo4 <= {i3[(N+1)*4*2-1:(N+1)*4],3'b0,|i3[(N+1)*4-1:0]};
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2'b01: mo4 <= {i3[(N+1)*4*2-1:(N+1)*4],3'b0,|i3[(N+1)*4-1:0]};
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default: mo4 <= {i3[(N+1)*4*2-1-4:N*4],3'b0,|i3[N*4-1:0]};
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default: mo4 <= {i3[(N+1)*4*2-1-4:N*4],3'b0,|i3[N*4-1:0]};
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endcase
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endcase
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always @(posedge clk)
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always @(posedge clk)
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if(ce)
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if(ce)
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casez({zeroMan3,incExpByOne3})
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casez({zeroMan3,incExpByOne3})
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2'b1?: inexact4 <= 1'd0;
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2'b1?: inexact4 <= 1'd0;
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2'b01: inexact4 <= |i3[(N+1)*4-1:0];
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2'b01: inexact4 <= |i3[(N+1)*4-1:0];
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default: inexact4 <= |i3[N*4-1:0];
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default: inexact4 <= |i3[N*4-1:0];
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endcase
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endcase
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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// Clock edge #5
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// Clock edge #5
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// - count leading zeros
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// - count leading zeros
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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reg [7:0] leadingZeros5;
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reg [7:0] leadingZeros5;
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wire [15:0] xo5;
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wire [15:0] xo5;
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wire xInf5;
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wire xInf5;
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delay #(.WID(16),.DEP(2)) u51 (.clk(clk), .ce(ce), .i(xo3), .o(xo5));
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delay #(.WID(16),.DEP(2)) u51 (.clk(clk), .ce(ce), .i(xo3), .o(xo5));
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delay #(.WID(1),.DEP(3)) u52 (.clk(clk), .ce(ce), .i(xInf2c), .o(xInf5) );
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delay #(.WID(1),.DEP(3)) u52 (.clk(clk), .ce(ce), .i(xInf2c), .o(xInf5) );
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/* Lookup table based leading zero count modules give slightly better
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/* Lookup table based leading zero count modules give slightly better
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performance but cases must be coded.
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performance but cases must be coded.
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generate
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generate
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begin
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begin
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if (FPWID <= 32) begin
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if (FPWID <= 32) begin
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cntlz32Reg clz0 (.clk(clk), .ce(ce), .i({mo4,4'b0}), .o(leadingZeros5) );
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cntlz32Reg clz0 (.clk(clk), .ce(ce), .i({mo4,4'b0}), .o(leadingZeros5) );
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assign leadingZeros5[7:6] = 2'b00;
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assign leadingZeros5[7:6] = 2'b00;
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end
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end
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else if (FPWID<=64) begin
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else if (FPWID<=64) begin
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assign leadingZeros5[7] = 1'b0;
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assign leadingZeros5[7] = 1'b0;
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cntlz64Reg clz0 (.clk(clk), .ce(ce), .i({mo4,7'h0}), .o(leadingZeros5) );
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cntlz64Reg clz0 (.clk(clk), .ce(ce), .i({mo4,7'h0}), .o(leadingZeros5) );
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end
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end
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else if (FPWID<=80) begin
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else if (FPWID<=80) begin
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assign leadingZeros5[7] = 1'b0;
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assign leadingZeros5[7] = 1'b0;
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cntlz80Reg clz0 (.clk(clk), .ce(ce), .i({mo4,11'b0}), .o(leadingZeros5) );
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cntlz80Reg clz0 (.clk(clk), .ce(ce), .i({mo4,11'b0}), .o(leadingZeros5) );
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end
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end
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else if (FPWID<=84) begin
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else if (FPWID<=84) begin
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assign leadingZeros5[7] = 1'b0;
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assign leadingZeros5[7] = 1'b0;
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cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo4,23'b0}), .o(leadingZeros5) );
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cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo4,23'b0}), .o(leadingZeros5) );
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end
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end
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else if (FPWID<=96) begin
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else if (FPWID<=96) begin
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assign leadingZeros5[7] = 1'b0;
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assign leadingZeros5[7] = 1'b0;
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cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo4,11'b0}), .o(leadingZeros5) );
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cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo4,11'b0}), .o(leadingZeros5) );
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end
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end
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else if (FPWID<=128)
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else if (FPWID<=128)
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cntlz128Reg clz0 (.clk(clk), .ce(ce), .i({mo4,11'b0}), .o(leadingZeros5) );
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cntlz128Reg clz0 (.clk(clk), .ce(ce), .i({mo4,11'b0}), .o(leadingZeros5) );
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end
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end
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endgenerate
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endgenerate
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*/
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*/
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// Sideways add.
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// Sideways add.
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// Normally there would be only one to two leading zeros. It is tempting then
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// Normally there would be only one to two leading zeros. It is tempting then
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// to check for only one or two. But, denormalized numbers might have more
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// to check for only one or two. But, denormalized numbers might have more
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// leading zeros. If denormals were not supported this could be made smaller
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// leading zeros. If denormals were not supported this could be made smaller
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// and faster.
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// and faster.
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`ifdef SUPPORT_DENORMALS
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`ifdef SUPPORT_DENORMALS
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reg [7:0] lzc;
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reg [7:0] lzc;
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reg got_one;
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reg got_one;
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always @*
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always @*
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begin
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begin
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got_one = 1'b0;
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got_one = 1'b0;
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lzc = 8'h00;
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lzc = 8'h00;
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for (n = (N+2)*4-1; n >= 0; n = n - 4) begin
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for (n = (N+2)*4-1; n >= 0; n = n - 4) begin
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if (!got_one) begin
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if (!got_one) begin
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if (mo4[n]|mo4[n-1]|mo4[n-2]|mo4[n-3])
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if (mo4[n]|mo4[n-1]|mo4[n-2]|mo4[n-3])
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got_one = 1'b1;
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got_one = 1'b1;
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else
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else
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lzc = lzc + 1'b1;
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lzc = lzc + 1'b1;
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end
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end
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end
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end
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end
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end
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always @(posedge clk)
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always @(posedge clk)
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if (ce) leadingZeros5 <= lzc;
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if (ce) leadingZeros5 <= lzc;
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`else
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`else
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always @(posedge clk)
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always @(posedge clk)
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if (ce)
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if (ce)
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casez(mo4[(N+1)*4-1:(N-1)*4-1])
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casez(mo4[(N+1)*4-1:(N-1)*4-1])
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8'h00000000: leadingZeros5 <= 8'd2;
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8'b00000000: leadingZeros5 <= 8'd2;
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8'h0000????: leadingZeros5 <= 8'd1;
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8'b0000????: leadingZeros5 <= 8'd1;
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default: leadingZeros5 <= 8'd0;
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default: leadingZeros5 <= 8'd0;
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endcase
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endcase
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`endif
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`endif
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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// Clock edge #6
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// Clock edge #6
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// - Compute how much we want to decrement exponent by
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// - Compute how much we want to decrement exponent by
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// - compute amount to shift left and right
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// - compute amount to shift left and right
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// - at infinity the exponent can't be incremented, so we can't shift right
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// - at infinity the exponent can't be incremented, so we can't shift right
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// otherwise it was an underflow situation so the exponent was negative
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// otherwise it was an underflow situation so the exponent was negative
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// shift amount needs to be negated for shift register
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// shift amount needs to be negated for shift register
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// If the exponent underflowed, then the shift direction must be to the
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// If the exponent underflowed, then the shift direction must be to the
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// right regardless of mantissa bits; the number is denormalized.
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// right regardless of mantissa bits; the number is denormalized.
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// Otherwise the shift direction must be to the left.
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// Otherwise the shift direction must be to the left.
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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reg [7:0] lshiftAmt6;
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reg [7:0] lshiftAmt6;
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reg [7:0] rshiftAmt6;
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reg [7:0] rshiftAmt6;
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wire rightOrLeft6; // 0=left,1=right
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wire rightOrLeft6; // 0=left,1=right
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wire xInf6;
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wire xInf6;
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wire [15:0] xo6;
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wire [15:0] xo6;
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wire [(N+2)*4-1:0] mo6;
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wire [(N+2)*4-1:0] mo6;
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wire zeroMan6;
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wire zeroMan6;
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vtdl #(1) u61 (.clk(clk), .ce(ce), .a(4'd5), .d(under_i), .q(rightOrLeft6) );
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vtdl #(1) u61 (.clk(clk), .ce(ce), .a(4'd5), .d(under_i), .q(rightOrLeft6) );
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delay #(.WID(16),.DEP(1)) u62 (.clk(clk), .ce(ce), .i(xo5), .o(xo6));
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delay #(.WID(16),.DEP(1)) u62 (.clk(clk), .ce(ce), .i(xo5), .o(xo6));
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delay #(.WID((N+2)*4),.DEP(2)) u63 (.clk(clk), .ce(ce), .i(mo4), .o(mo6) );
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delay #(.WID((N+2)*4),.DEP(2)) u63 (.clk(clk), .ce(ce), .i(mo4), .o(mo6) );
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delay #(.WID(1),.DEP(1)) u64 (.clk(clk), .ce(ce), .i(xInf5), .o(xInf6) );
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delay #(.WID(1),.DEP(1)) u64 (.clk(clk), .ce(ce), .i(xInf5), .o(xInf6) );
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delay #(.WID(1),.DEP(3)) u65 (.clk(clk), .ce(ce), .i(zeroMan3), .o(zeroMan6));
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delay #(.WID(1),.DEP(3)) u65 (.clk(clk), .ce(ce), .i(zeroMan3), .o(zeroMan6));
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delay #(.WID(1),.DEP(5)) u66 (.clk(clk), .ce(ce), .i(sx0), .o(sx5) );
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delay #(.WID(1),.DEP(5)) u66 (.clk(clk), .ce(ce), .i(sx0), .o(sx5) );
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|
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wire [13:0] xo5d = xo5[3:0] + xo5[7:4] * 10 + xo5[11:8] * 100 + xo5[15:12] * 1000;
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wire [13:0] xo5d = xo5[3:0] + xo5[7:4] * 10 + xo5[11:8] * 100 + xo5[15:12] * 1000;
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|
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always @(posedge clk)
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always @(posedge clk)
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if (ce) lshiftAmt6 <= {leadingZeros5 > xo5d ? xo5d : leadingZeros5,2'b0};
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if (ce) lshiftAmt6 <= {leadingZeros5 > xo5d ? xo5d : leadingZeros5,2'b0};
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|
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always @(posedge clk)
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always @(posedge clk)
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if (ce) rshiftAmt6 <= xInf5 ? 1'd0 : sx5 ? 1'd0 : xo5d > N ? N*4 : {xo5d[5:0],2'b00}; // xo2 is negative !
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if (ce) rshiftAmt6 <= xInf5 ? 1'd0 : sx5 ? 1'd0 : xo5d > N ? N*4 : {xo5d[5:0],2'b00}; // xo2 is negative !
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|
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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// Clock edge #7
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// Clock edge #7
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// - figure exponent
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// - figure exponent
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// - shift mantissa
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// - shift mantissa
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// - figure sticky bit
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// - figure sticky bit
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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|
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reg [15:0] xo7;
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reg [15:0] xo7;
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wire rightOrLeft7;
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wire rightOrLeft7;
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reg [(N+2)*4-1:0] mo7l, mo7r;
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reg [(N+2)*4-1:0] mo7l, mo7r;
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reg St6,St7;
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reg St6,St7;
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delay #(.WID(1),.DEP(1)) u71 (.clk(clk), .ce(ce), .i(rightOrLeft6), .o(rightOrLeft7));
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delay #(.WID(1),.DEP(1)) u71 (.clk(clk), .ce(ce), .i(rightOrLeft6), .o(rightOrLeft7));
|
|
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wire [11:0] lshftAmtBCD;
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wire [11:0] lshftAmtBCD;
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wire [15:0] xo7d;
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wire [15:0] xo7d;
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BinToBCD ubbcd1 (lshiftAmt6, lshftAmtBCD);
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BinToBCD ubbcd1 (lshiftAmt6, lshftAmtBCD);
|
BCDSubN #(.N(4)) ubcdsn1
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BCDSubN #(.N(4)) ubcdsn1
|
(
|
(
|
.ci(1'b0),
|
.ci(1'b0),
|
.a(xo6),
|
.a(xo6),
|
.b({4'h0,lshftAmtBCD}),
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.b({4'h0,lshftAmtBCD}),
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.o(xo7d),
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.o(xo7d),
|
.co()
|
.co()
|
);
|
);
|
|
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
if (ce)
|
if (ce)
|
xo7 <= zeroMan6 ? xo6 :
|
xo7 <= zeroMan6 ? xo6 :
|
xInf6 ? xo6 : // an infinite exponent is either a NaN or infinity; no need to change
|
xInf6 ? xo6 : // an infinite exponent is either a NaN or infinity; no need to change
|
rightOrLeft6 ? 1'd0 : // on a right shift, the exponent was negative, it's being made to zero
|
rightOrLeft6 ? 1'd0 : // on a right shift, the exponent was negative, it's being made to zero
|
xo7d; // on a left shift, the exponent can't be decremented below zero
|
xo7d; // on a left shift, the exponent can't be decremented below zero
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
if (ce) mo7r <= mo6 >> rshiftAmt6;
|
if (ce) mo7r <= mo6 >> rshiftAmt6;
|
always @(posedge clk)
|
always @(posedge clk)
|
if (ce) mo7l <= mo6 << lshiftAmt6;
|
if (ce) mo7l <= mo6 << lshiftAmt6;
|
|
|
// The sticky bit is set if the bits shifted out on a right shift are set.
|
// The sticky bit is set if the bits shifted out on a right shift are set.
|
always @*
|
always @*
|
begin
|
begin
|
St6 = 1'b0;
|
St6 = 1'b0;
|
for (n = 0; n < (N+2)*4; n = n + 1)
|
for (n = 0; n < (N+2)*4; n = n + 1)
|
if (n <= rshiftAmt6 + 1) St6 = St6|mo6[n];
|
if (n <= rshiftAmt6 + 1) St6 = St6|mo6[n];
|
end
|
end
|
always @(posedge clk)
|
always @(posedge clk)
|
if (ce) St7 <= St6;
|
if (ce) St7 <= St6;
|
|
|
// ----------------------------------------------------------------------------
|
// ----------------------------------------------------------------------------
|
// Clock edge #8
|
// Clock edge #8
|
// - select mantissa
|
// - select mantissa
|
// ----------------------------------------------------------------------------
|
// ----------------------------------------------------------------------------
|
|
|
wire so,sxo,nano,info;
|
wire so,sxo,nano,info;
|
wire [15:0] xo;
|
wire [15:0] xo;
|
reg [(N+2)*4-1:0] mo;
|
reg [(N+2)*4-1:0] mo;
|
vtdl #(1) u81 (.clk(clk), .ce(ce), .a(4'd7), .d(so0), .q(so) );
|
vtdl #(1) u81 (.clk(clk), .ce(ce), .a(4'd7), .d(so0), .q(so) );
|
delay #(.WID(16),.DEP(1)) u82 (.clk(clk), .ce(ce), .i(xo7), .o(xo));
|
delay #(.WID(16),.DEP(1)) u82 (.clk(clk), .ce(ce), .i(xo7), .o(xo));
|
vtdl #(.WID(1)) u83 (.clk(clk), .ce(ce), .a(4'd3), .d(inexact4), .q(inexact_o));
|
vtdl #(.WID(1)) u83 (.clk(clk), .ce(ce), .a(4'd3), .d(inexact4), .q(inexact_o));
|
delay #(.WID(1),.DEP(1)) u84 (.clk(clk), .ce(ce), .i(rightOrLeft7), .o(under_o));
|
delay #(.WID(1),.DEP(1)) u84 (.clk(clk), .ce(ce), .i(rightOrLeft7), .o(under_o));
|
vtdl #(1) u85 (.clk(clk), .ce(ce), .a(4'd7), .d(sx0), .q(sxo) );
|
vtdl #(1) u85 (.clk(clk), .ce(ce), .a(4'd7), .d(sx0), .q(sxo) );
|
vtdl #(1) u86 (.clk(clk), .ce(ce), .a(4'd7), .d(nan0), .q(nano) );
|
vtdl #(1) u86 (.clk(clk), .ce(ce), .a(4'd7), .d(nan0), .q(nano) );
|
vtdl #(1) u87 (.clk(clk), .ce(ce), .a(4'd7), .d(inf0), .q(info) );
|
vtdl #(1) u87 (.clk(clk), .ce(ce), .a(4'd7), .d(inf0), .q(info) );
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
if (ce) mo <= rightOrLeft7 ? mo7r|{St7,4'b0} : mo7l;
|
if (ce) mo <= rightOrLeft7 ? mo7r|{St7,4'b0} : mo7l;
|
|
|
assign o = {nano,so,info,sxo,xo,mo[(N+2)*4-1:4]};
|
assign o = {nano,so,info,sxo,xo,mo[(N+2)*4-1:4]};
|
|
|
endmodule
|
endmodule
|
|
|
|
|
