// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2006-2022 Robert Finch, Waterloo
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// \\__/ o\ (C) 2006-2022 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// \/_// robfinch@finitron.ca
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// ||
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// ||
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//
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//
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// dfdiv.v
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// dfdiv.v
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// Decimal Float divider primitive
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// Decimal Float divider primitive
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//
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//
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// BSD 3-Clause License
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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// 1. Redistributions of source code must retain the above copyright notice, this
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// list of conditions and the following disclaimer.
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// list of conditions and the following disclaimer.
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//
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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//
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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// this software without specific prior written permission.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// ============================================================================
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// ============================================================================
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module dfdiv(clk, ld, a, b, q, r, done, lzcnt);
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module dfdiv(clk, ld, a, b, q, r, done, lzcnt);
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parameter N=33;
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parameter N=33;
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localparam FPWID = N*4;
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localparam FPWID = N*4;
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parameter RADIX = 10;
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parameter RADIX = 10;
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localparam FPWID1 = FPWID;//((FPWID+2)/3)*3; // make FPWIDth a multiple of three
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localparam FPWID1 = FPWID;//((FPWID+2)/3)*3; // make FPWIDth a multiple of three
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localparam DMSB = FPWID1-1;
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localparam DMSB = FPWID1-1;
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input clk;
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input clk;
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input ld;
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input ld;
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input [FPWID-1:0] a;
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input [FPWID-1:0] a;
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input [FPWID-1:0] b;
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input [FPWID-1:0] b;
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output reg [FPWID*2-1:0] q;
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output reg [FPWID*2-1:0] q;
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output reg [FPWID-1:0] r;
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output reg [FPWID-1:0] r;
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output reg done;
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output reg done;
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output reg [7:0] lzcnt; // Leading zero digit count as a BCD number
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output reg [7:0] lzcnt; // Leading zero digit count as a BCD number
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reg [1:0] st;
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reg [1:0] st;
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parameter IDLE = 2'd0;
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parameter IDLE = 2'd0;
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parameter SUBN = 2'd1;
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parameter SUBN = 2'd1;
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parameter DONE = 2'd2;
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parameter DONE = 2'd2;
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reg [3:0] cnt; // iteration count
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reg [3:0] cnt; // iteration count
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wire [3:0] cntm1 = cnt;//cnt==4'd0 ? 4'd9 : cnt-1'd1;
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wire [3:0] cntm1 = cnt;//cnt==4'd0 ? 4'd9 : cnt-1'd1;
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reg [7:0] dcnt; // digit count
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reg [7:0] dcnt; // digit count
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reg [15:0] clkcnt;
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reg [15:0] clkcnt;
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reg [5:0] digcnt;
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reg [5:0] digcnt;
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reg [FPWID*2-1:0] qi;
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reg [FPWID*2-1:0] qi;
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reg [FPWID+3:0] ri;
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reg [FPWID+3:0] ri;
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reg [FPWID-1:0] bi;
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reg [FPWID-1:0] bi;
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wire sgn;
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wire sgn;
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wire [FPWID+3:0] dif;
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wire [FPWID+3:0] dif;
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reg gotnz; // got a non-zero digit
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reg gotnz; // got a non-zero digit
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generate begin : gSub
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generate begin : gSub
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BCDSubtract #(.N(N+1)) ubcds1
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BCDSubtract #(.N(N+1)) ubcds1
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(
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(
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.clk(clk),
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.clk(clk),
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.a(ri),
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.a(ri),
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.b({4'b0,bi}),
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.b({4'b0,bi}),
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.o(dif),
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.o(dif),
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.sgn(sgn)
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.sgn(sgn)
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);
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);
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end
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end
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endgenerate
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endgenerate
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reg nz;
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reg nz;
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reg [N-1:0] zc;
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reg [N*2-1:0] zc;
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genvar g;
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genvar g;
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generate begin : glzcnt
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generate begin : glzcnt
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for (g = N-1; g >= 0; g = g - 1)
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for (g = N*2-1; g >= 0; g = g - 1)
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always_comb
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always_comb
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zc[g] = qi[g*4+3+N*4:g*4+N*4]==0;
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zc[g] = qi[g*4+3:g*4]==0;
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end
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end
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endgenerate
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endgenerate
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integer n;
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integer n;
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always_comb
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always_comb
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begin
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begin
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nz = 1'b0;
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nz = 1'b0;
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lzcnt = 'd0;
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lzcnt = 'd0;
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for (n = N-1; n >= 0; n = n - 1)
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for (n = N*2-1; n >= 0; n = n - 1)
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begin
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begin
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nz = nz | ~zc[n];
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nz = nz | ~zc[n];
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if (!nz)
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if (!nz)
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lzcnt = lzcnt + 1;
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lzcnt = lzcnt + 1;
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end
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end
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end
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end
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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case(st)
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case(st)
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IDLE:
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IDLE:
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begin
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begin
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qi <= 'd0;
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qi <= 'd0;
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ri <= 'd0;
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ri <= 'd0;
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end
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end
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SUBN:
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SUBN:
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begin
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begin
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digcnt <= digcnt - 1'd1;
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digcnt <= digcnt - 1'd1;
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if (digcnt=='d0) begin
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if (digcnt=='d0) begin
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clkcnt <= clkcnt + 1'd1;
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clkcnt <= clkcnt + 1'd1;
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digcnt <= 6'd10;
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digcnt <= 6'd10;
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if (bi > ri) begin
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if (bi > ri) begin
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ri <= {ri,qi[FPWID*2-1:FPWID*2-4]};
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ri <= {ri,qi[FPWID*2-1:FPWID*2-4]};
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qi <= {qi[FPWID*2-5:0],cnt};
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qi <= {qi[FPWID*2-5:0],cnt};
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cnt <= 4'd0;
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cnt <= 4'd0;
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dcnt <= dcnt - 1'd1;
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dcnt <= dcnt - 1'd1;
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if (dcnt=='d0)
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if (dcnt=='d0)
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st <= DONE;
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st <= DONE;
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end
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end
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else begin
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else begin
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if (clkcnt > 600 && 0) begin
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if (clkcnt > 600 && 0) begin
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ri <= {ri,qi[FPWID*2-1:FPWID*2-4]};
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ri <= {ri,qi[FPWID*2-1:FPWID*2-4]};
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qi <= {qi[FPWID*2-5:0],cntm1};
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qi <= {qi[FPWID*2-5:0],cntm1};
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cnt <= 4'd0;
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cnt <= 4'd0;
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dcnt <= dcnt - 1'd1;
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dcnt <= dcnt - 1'd1;
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if (dcnt==6'd0)
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if (dcnt==6'd0)
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st <= DONE;
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st <= DONE;
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end
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end
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else
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else
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begin
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begin
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ri <= dif;//N[0] ? dif : dif[FPWID+4-1:4];
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ri <= dif;
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cnt <= cnt + 1'd1;
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cnt <= cnt + 1'd1;
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end
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end
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end
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end
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end
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end
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end
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end
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DONE:
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DONE:
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begin
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begin
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q <= qi;
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q <= qi;
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r <= ri;
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r <= ri;
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done <= 1'b1;
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done <= 1'b1;
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end
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end
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default:
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default:
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st <= IDLE;
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st <= IDLE;
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endcase
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endcase
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if (ld) begin
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if (ld) begin
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clkcnt <= 10'd0;
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clkcnt <= 10'd0;
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cnt <= 4'd0;
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cnt <= 4'd0;
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digcnt <= 6'd10;
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digcnt <= 6'd10;
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dcnt <= $ceil(FPWID*2/4);
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dcnt <= $ceil(FPWID*2/4);
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qi <= {a,{FPWID{1'd0}}};
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qi <= {a,{FPWID{1'd0}}};
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ri <= {FPWID{1'd0}};
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ri <= {FPWID{1'd0}};
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bi <= b;
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bi <= b;
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st <= SUBN;
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st <= SUBN;
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done <= 1'b0;
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done <= 1'b0;
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end
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end
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end
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end
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endmodule
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endmodule
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module dfdiv_tb();
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module dfdiv_tb();
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reg clk;
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reg clk;
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reg ld;
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reg ld;
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reg [135:0] a, b;
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reg [135:0] a, b;
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wire [271:0] q;
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wire [271:0] q;
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wire [135:0] r;
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wire [135:0] r;
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wire [7:0] lzcnt;
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wire [7:0] lzcnt;
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initial begin
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initial begin
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clk = 1'b0;
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clk = 1'b0;
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ld = 1'b0;
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ld = 1'b0;
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a = 136'h50_00000000_00000000_00000000_00000000;
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a = 136'h50_00000000_00000000_00000000_00000000;
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b = 136'h50_00000000_00000000_00000000_00000000;
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b = 136'h50_00000000_00000000_00000000_00000000;
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#20 ld = 1'b1;
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#20 ld = 1'b1;
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#40 ld = 1'b0;
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#40 ld = 1'b0;
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end
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end
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always #5 clk = ~clk;
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always #5 clk = ~clk;
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dfdiv #(.N(34)) u1 (
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dfdiv #(.N(34)) u1 (
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.clk(clk),
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.clk(clk),
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.ld(ld),
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.ld(ld),
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.a(a),
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.a(a),
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.b(b),
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.b(b),
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.q(q),
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.q(q),
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.r(r),
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.r(r),
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.done(done),
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.done(done),
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.lzcnt(lzcnt)
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.lzcnt(lzcnt)
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);
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);
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endmodule
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endmodule
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