URL
https://opencores.org/ocsvn/galois_lfsr/galois_lfsr/trunk
[/] [galois_lfsr/] [trunk/] [rtl/] [user.vhdl] - Diff between revs 7 and 8
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| Rev 7 |
Rev 8 |
| Line 38... |
Line 38... |
library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; use ieee.math_real.all;
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library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; use ieee.math_real.all;
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/* Enable for synthesis; comment out for simulation.
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/* Enable for synthesis; comment out for simulation.
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For this design, we just need boolean_vector. This is already included in Questa/ModelSim,
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For this design, we just need boolean_vector. This is already included in Questa/ModelSim,
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but Quartus doesn't yet support this.
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but Quartus doesn't yet support this.
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*/
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*/
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use work.types.all;
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--use work.types.all;
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entity user is
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entity user is
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generic(
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generic(
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parallelLoad:boolean:=false;
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parallelLoad:boolean:=false;
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tapVector:boolean_vector:=(
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tapVector:boolean_vector:=(
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| Line 52... |
Line 52... |
0|1|2|8=>true, 7 downto 3=>false
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0|1|2|8=>true, 7 downto 3=>false
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)
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)
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);
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);
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port(
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port(
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/* Comment-out for simulation. */
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/* Comment-out for simulation. */
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clk,reset:in std_ulogic;
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-- clk,reset:in std_ulogic;
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msg:in unsigned(tapVector'high downto 0):=9x"57";
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msg:in unsigned(tapVector'high downto 0):=9x"57";
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crc32:out unsigned(31 downto 0):=(others=>'0')
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crc32:out unsigned(31 downto 0):=(others=>'0')
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);
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);
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end entity user;
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end entity user;
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