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[/] [i2c/] [trunk/] [rtl/] [verilog/] [i2c_master_top.v] - Diff between revs 68 and 73
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// $Author: rherveille $
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// $Author: rherveille $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// Revision 1.11 2005/02/27 09:26:24 rherveille
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// Revision 1.11 2005/02/27 09:26:24 rherveille
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// Fixed register overwrite issue.
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// Fixed register overwrite issue.
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// Removed full_case pragma, replaced it by a default statement.
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// Removed full_case pragma, replaced it by a default statement.
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//
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//
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// Revision 1.10 2003/09/01 10:34:38 rherveille
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// Revision 1.10 2003/09/01 10:34:38 rherveille
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// generate internal reset
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// generate internal reset
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wire rst_i = arst_i ^ ARST_LVL;
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wire rst_i = arst_i ^ ARST_LVL;
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// generate wishbone signals
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// generate wishbone signals
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wire wb_wacc = wb_cyc_i & wb_stb_i & wb_we_i;
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wire wb_wacc = wb_we_i & wb_ack_o;
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// generate acknowledge output signal
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// generate acknowledge output signal
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always @(posedge wb_clk_i)
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always @(posedge wb_clk_i)
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wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored
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wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored
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