Line 1... |
Line 1... |
---------------------------------------------------------------------
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---------------------------------------------------------------------
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---- ----
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---- ----
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---- WISHBONE revB2 compl. I2C Master Core; bit-controller ----
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---- WISHBONE revB2 I2C Master Core; bit-controller ----
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---- ----
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---- ----
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---- ----
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---- ----
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---- Author: Richard Herveille ----
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---- Author: Richard Herveille ----
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---- richard@asics.ws ----
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---- richard@asics.ws ----
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---- www.asics.ws ----
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---- www.asics.ws ----
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Line 35... |
Line 35... |
---- ----
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---- ----
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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|
|
-- CVS Log
|
-- CVS Log
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--
|
--
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-- $Id: i2c_master_bit_ctrl.vhd,v 1.3 2002-10-30 18:09:53 rherveille Exp $
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-- $Id: i2c_master_bit_ctrl.vhd,v 1.4 2002-11-30 22:24:37 rherveille Exp $
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--
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--
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-- $Date: 2002-10-30 18:09:53 $
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-- $Date: 2002-11-30 22:24:37 $
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-- $Revision: 1.3 $
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-- $Revision: 1.4 $
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-- $Author: rherveille $
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-- $Author: rherveille $
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-- $Locker: $
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-- $Locker: $
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-- $State: Exp $
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-- $State: Exp $
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--
|
--
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-- Change History:
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-- Change History:
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.3 2002/10/30 18:09:53 rherveille
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|
-- Fixed some reported minor start/stop generation timing issuess.
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|
--
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-- Revision 1.2 2002/06/15 07:37:04 rherveille
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-- Revision 1.2 2002/06/15 07:37:04 rherveille
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-- Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
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-- Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
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--
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--
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-- Revision 1.1 2001/11/05 12:02:33 rherveille
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-- Revision 1.1 2001/11/05 12:02:33 rherveille
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-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
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-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
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Line 99... |
Line 102... |
library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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|
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entity i2c_master_bit_ctrl is
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entity i2c_master_bit_ctrl is
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generic(
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|
Tcq : time := 1 ns
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);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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nReset : in std_logic;
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nReset : in std_logic;
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ena : in std_logic; -- core enable signal
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ena : in std_logic; -- core enable signal
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Line 151... |
Line 151... |
begin
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begin
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-- synchronize SCL and SDA inputs
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-- synchronize SCL and SDA inputs
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synch_scl_sda: process(clk)
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synch_scl_sda: process(clk)
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begin
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begin
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if (clk'event and clk = '1') then
|
if (clk'event and clk = '1') then
|
sSCL <= scl_i after Tcq;
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sSCL <= scl_i;
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sSDA <= sda_i after Tcq;
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sSDA <= sda_i;
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end if;
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end if;
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end process synch_SCL_SDA;
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end process synch_SCL_SDA;
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-- delay scl_oen
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-- delay scl_oen
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process (clk)
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process (clk)
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begin
|
begin
|
if (clk'event and clk = '1') then
|
if (clk'event and clk = '1') then
|
dscl_oen <= iscl_oen after Tcq;
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dscl_oen <= iscl_oen;
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end if;
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end if;
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end process;
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end process;
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|
-- whenever the slave is not ready it can delay the cycle by pulling SCL low
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-- whenever the slave is not ready it can delay the cycle by pulling SCL low
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slave_wait <= dscl_oen and not sSCL;
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slave_wait <= dscl_oen and not sSCL;
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-- generate clk enable signal
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-- generate clk enable signal
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gen_clken: process(clk, nReset)
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gen_clken: process(clk, nReset)
|
begin
|
begin
|
if (nReset = '0') then
|
if (nReset = '0') then
|
cnt <= (others => '0') after Tcq;
|
cnt <= (others => '0');
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clk_en <= '1' after Tcq;
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clk_en <= '1';
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elsif (clk'event and clk = '1') then
|
elsif (clk'event and clk = '1') then
|
if (rst = '1') then
|
if (rst = '1') then
|
cnt <= (others => '0') after Tcq;
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cnt <= (others => '0');
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clk_en <= '1' after Tcq;
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clk_en <= '1';
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else
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else
|
if ( (cnt = 0) or (ena = '0') ) then
|
if ( (cnt = 0) or (ena = '0') ) then
|
clk_en <= '1' after Tcq;
|
clk_en <= '1';
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cnt <= clk_cnt after Tcq;
|
cnt <= clk_cnt;
|
else
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else
|
if (slave_wait = '0') then
|
if (slave_wait = '0') then
|
cnt <= cnt -1 after Tcq;
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cnt <= cnt -1;
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end if;
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end if;
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clk_en <= '0' after Tcq;
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clk_en <= '0';
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end if;
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end if;
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end if;
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end if;
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end if;
|
end if;
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end process gen_clken;
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end process gen_clken;
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Line 216... |
Line 216... |
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-- generate bus busy signal
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-- generate bus busy signal
|
gen_busy: process(clk, nReset)
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gen_busy: process(clk, nReset)
|
begin
|
begin
|
if (nReset = '0') then
|
if (nReset = '0') then
|
ibusy <= '0' after Tcq;
|
ibusy <= '0';
|
elsif (clk'event and clk = '1') then
|
elsif (clk'event and clk = '1') then
|
if (rst = '1') then
|
if (rst = '1') then
|
ibusy <= '0' after Tcq;
|
ibusy <= '0';
|
else
|
else
|
ibusy <= (sta_condition or ibusy) and not sto_condition after Tcq;
|
ibusy <= (sta_condition or ibusy) and not sto_condition;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process gen_busy;
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end process gen_busy;
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-- assign output
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-- assign output
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Line 233... |
Line 233... |
end block bus_status_ctrl;
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end block bus_status_ctrl;
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-- generate statemachine
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-- generate statemachine
|
nxt_state_decoder : process (clk, nReset, c_state, cmd)
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nxt_state_decoder : process (clk, nReset, c_state, cmd)
|
variable nxt_state : states;
|
|
variable icmd_ack, store_sda : std_logic;
|
|
begin
|
begin
|
nxt_state := c_state;
|
if (nReset = '0') then
|
|
c_state <= idle;
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icmd_ack := '0'; -- default no acknowledge
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cmd_ack <= '0';
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dout <= '0';
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store_sda := '0';
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iscl_oen <= '1';
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isda_oen <= '1';
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|
elsif (clk'event and clk = '1') then
|
|
if (rst = '1') then
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c_state <= idle;
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cmd_ack <= '0';
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dout <= '0';
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iscl_oen <= '1';
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isda_oen <= '1';
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|
else
|
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cmd_ack <= '0'; -- default no acknowledge
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|
|
|
if (clk_en = '1') then
|
case (c_state) is
|
case (c_state) is
|
-- idle
|
-- idle
|
when idle =>
|
when idle =>
|
case cmd is
|
case cmd is
|
when I2C_CMD_START =>
|
when I2C_CMD_START => c_state <= start_a;
|
nxt_state := start_a;
|
when I2C_CMD_STOP => c_state <= stop_a;
|
|
when I2C_CMD_WRITE => c_state <= wr_a;
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when I2C_CMD_STOP =>
|
when I2C_CMD_READ => c_state <= rd_a;
|
nxt_state := stop_a;
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when others => c_state <= idle; -- NOP command
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|
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when I2C_CMD_WRITE =>
|
|
nxt_state := wr_a;
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|
|
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when I2C_CMD_READ =>
|
|
nxt_state := rd_a;
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|
|
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when others => -- NOP command
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nxt_state := idle;
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|
end case;
|
end case;
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|
|
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iscl_oen <= iscl_oen; -- keep SCL in same state
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isda_oen <= isda_oen; -- keep SDA in same state
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|
-- start
|
-- start
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when start_a =>
|
when start_a =>
|
nxt_state := start_b;
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c_state <= start_b;
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iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)
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isda_oen <= '1'; -- set SDA high
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|
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when start_b =>
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when start_b =>
|
nxt_state := start_c;
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c_state <= start_c;
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iscl_oen <= '1'; -- set SCL high
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isda_oen <= '1'; -- keep SDA high
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|
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when start_c =>
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when start_c =>
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nxt_state := start_d;
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c_state <= start_d;
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iscl_oen <= '1'; -- keep SCL high
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isda_oen <= '0'; -- set SDA low
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when start_d =>
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when start_d =>
|
nxt_state := start_e;
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c_state <= start_e;
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iscl_oen <= '1'; -- keep SCL high
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isda_oen <= '0'; -- keep SDA low
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when start_e =>
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when start_e =>
|
nxt_state := idle;
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c_state <= idle;
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icmd_ack := '1'; -- command completed
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cmd_ack <= '1'; -- command completed
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iscl_oen <= '0'; -- set SCL low
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isda_oen <= '0'; -- keep SDA low
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-- stop
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-- stop
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when stop_a =>
|
when stop_a =>
|
nxt_state := stop_b;
|
c_state <= stop_b;
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iscl_oen <= '0'; -- keep SCL disabled
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isda_oen <= '0'; -- set SDA low
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|
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when stop_b =>
|
when stop_b =>
|
nxt_state := stop_c;
|
c_state <= stop_c;
|
|
iscl_oen <= '1'; -- set SCL high
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isda_oen <= '0'; -- keep SDA low
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|
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when stop_c =>
|
when stop_c =>
|
nxt_state := stop_d;
|
c_state <= stop_d;
|
|
iscl_oen <= '1'; -- keep SCL high
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isda_oen <= '0'; -- keep SDA low
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|
|
when stop_d =>
|
when stop_d =>
|
nxt_state := idle;
|
c_state <= idle;
|
icmd_ack := '1'; -- command completed
|
cmd_ack <= '1'; -- command completed
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iscl_oen <= '1'; -- keep SCL high
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isda_oen <= '1'; -- set SDA high
|
|
|
-- read
|
-- read
|
when rd_a =>
|
when rd_a =>
|
nxt_state := rd_b;
|
c_state <= rd_b;
|
|
iscl_oen <= '0'; -- keep SCL low
|
|
isda_oen <= '1'; -- tri-state SDA
|
|
|
when rd_b =>
|
when rd_b =>
|
nxt_state := rd_c;
|
c_state <= rd_c;
|
|
iscl_oen <= '1'; -- set SCL high
|
|
isda_oen <= '1'; -- tri-state SDA
|
|
|
when rd_c =>
|
when rd_c =>
|
nxt_state := rd_d;
|
c_state <= rd_d;
|
store_sda := '1';
|
dout <= sSDA;
|
|
iscl_oen <= '1'; -- keep SCL high
|
|
isda_oen <= '1'; -- tri-state SDA
|
|
|
when rd_d =>
|
when rd_d =>
|
nxt_state := idle;
|
c_state <= idle;
|
icmd_ack := '1'; -- command completed
|
cmd_ack <= '1'; -- command completed
|
|
iscl_oen <= '0'; -- set SCL low
|
|
isda_oen <= '1'; -- tri-state SDA
|
|
|
-- write
|
-- write
|
when wr_a =>
|
when wr_a =>
|
nxt_state := wr_b;
|
c_state <= wr_b;
|
|
iscl_oen <= '0'; -- keep SCL low
|
|
isda_oen <= din; -- set SDA
|
|
|
when wr_b =>
|
when wr_b =>
|
nxt_state := wr_c;
|
c_state <= wr_c;
|
|
iscl_oen <= '1'; -- set SCL high
|
|
isda_oen <= din; -- keep SDA
|
|
|
when wr_c =>
|
when wr_c =>
|
nxt_state := wr_d;
|
c_state <= wr_d;
|
|
iscl_oen <= '1'; -- keep SCL high
|
|
isda_oen <= din; -- keep SDA
|
|
|
when wr_d =>
|
when wr_d =>
|
nxt_state := idle;
|
c_state <= idle;
|
icmd_ack := '1'; -- command completed
|
cmd_ack <= '1'; -- command completed
|
|
iscl_oen <= '0'; -- set SCL low
|
|
isda_oen <= din; -- keep SDA
|
|
|
end case;
|
when others =>
|
|
|
-- generate regs
|
|
if (nReset = '0') then
|
|
c_state <= idle after Tcq;
|
|
cmd_ack <= '0' after Tcq;
|
|
Dout <= '0' after Tcq;
|
|
elsif (clk'event and clk = '1') then
|
|
if (rst = '1') then
|
|
c_state <= idle after Tcq;
|
|
cmd_ack <= '0' after Tcq;
|
|
Dout <= '0' after Tcq;
|
|
elsif (clk_en = '1') then
|
|
c_state <= nxt_state after Tcq;
|
|
|
|
if (store_sda = '1') then
|
end case;
|
dout <= sSDA after Tcq;
|
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
cmd_ack <= icmd_ack and clk_en;
|
|
end if;
|
end if;
|
end process nxt_state_decoder;
|
end process nxt_state_decoder;
|
|
|
--
|
|
-- convert states to SCL and SDA signals
|
|
--
|
|
output_decoder: process (clk, nReset, c_state, iscl_oen, isda_oen, din)
|
|
variable iscl, isda : std_logic;
|
|
begin
|
|
case (c_state) is
|
|
-- idle
|
|
when idle =>
|
|
iscl := iscl_oen; -- keep SCL in same state
|
|
isda := isda_oen; -- keep SDA in same state
|
|
|
|
-- start
|
|
when start_a =>
|
|
iscl := iscl_oen; -- keep SCL in same state (for repeated start)
|
|
isda := '1'; -- set SDA high
|
|
|
|
when start_b =>
|
|
iscl := '1'; -- set SCL high
|
|
isda := '1'; -- keep SDA high
|
|
|
|
when start_c =>
|
|
iscl := '1'; -- keep SCL high
|
|
isda := '0'; -- set SDA low
|
|
|
|
when start_d =>
|
|
iscl := '1'; -- keep SCL high
|
|
isda := '0'; -- keep SDA low
|
|
|
|
when start_e =>
|
|
iscl := '0'; -- set SCL low
|
|
isda := '0'; -- keep SDA low
|
|
|
|
-- stop
|
|
when stop_a =>
|
|
iscl := '0'; -- keep SCL disabled
|
|
isda := '0'; -- set SDA low
|
|
|
|
when stop_b =>
|
|
iscl := '1'; -- set SCL high
|
|
isda := '0'; -- keep SDA low
|
|
|
|
when stop_c =>
|
|
iscl := '1'; -- keep SCL high
|
|
isda := '0'; -- keep SDA low
|
|
|
|
when stop_d =>
|
|
iscl := '1'; -- keep SCL high
|
|
isda := '1'; -- set SDA high
|
|
|
|
-- write
|
|
when wr_a =>
|
|
iscl := '0'; -- keep SCL low
|
|
isda := din; -- set SDA
|
|
|
|
when wr_b =>
|
|
iscl := '1'; -- set SCL high
|
|
isda := din; -- keep SDA
|
|
|
|
when wr_c =>
|
|
iscl := '1'; -- keep SCL high
|
|
isda := din; -- keep SDA
|
|
|
|
when wr_d =>
|
|
iscl := '0'; -- set SCL low
|
|
isda := din; -- keep SDA
|
|
|
|
-- read
|
|
when rd_a =>
|
|
iscl := '0'; -- keep SCL low
|
|
isda := '1'; -- tri-state SDA
|
|
|
|
when rd_b =>
|
|
iscl := '1'; -- set SCL high
|
|
isda := '1'; -- tri-state SDA
|
|
|
|
when rd_c =>
|
|
iscl := '1'; -- keep SCL high
|
|
isda := '1'; -- tri-state SDA
|
|
|
|
when rd_d =>
|
|
iscl := '0'; -- set SCL low
|
|
isda := '1'; -- tri-state SDA
|
|
end case;
|
|
|
|
-- generate registers
|
|
if (nReset = '0') then
|
|
iscl_oen <= '1' after Tcq;
|
|
isda_oen <= '1' after Tcq;
|
|
elsif (clk'event and clk = '1') then
|
|
if (rst = '1') then
|
|
iscl_oen <= '1' after Tcq;
|
|
isda_oen <= '1' after Tcq;
|
|
elsif (clk_en = '1') then
|
|
iscl_oen <= iscl after Tcq;
|
|
isda_oen <= isda after Tcq;
|
|
end if;
|
|
end if;
|
|
end process output_decoder;
|
|
|
|
-- assign outputs
|
-- assign outputs
|
scl_o <= '0';
|
scl_o <= '0';
|
scl_oen <= iscl_oen;
|
scl_oen <= iscl_oen;
|
sda_o <= '0';
|
sda_o <= '0';
|