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[/] [i2c/] [trunk/] [rtl/] [vhdl/] [i2c_master_bit_ctrl.vhd] - Diff between revs 24 and 27

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---------------------------------------------------------------------
---------------------------------------------------------------------
----                                                             ----
----                                                             ----
----  WISHBONE revB2 compl. I2C Master Core; bit-controller      ----
----  WISHBONE revB2 I2C Master Core; bit-controller             ----
----                                                             ----
----                                                             ----
----                                                             ----
----                                                             ----
----  Author: Richard Herveille                                  ----
----  Author: Richard Herveille                                  ----
----          richard@asics.ws                                   ----
----          richard@asics.ws                                   ----
----          www.asics.ws                                       ----
----          www.asics.ws                                       ----
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----                                                             ----
----                                                             ----
---------------------------------------------------------------------
---------------------------------------------------------------------
 
 
--  CVS Log
--  CVS Log
--
--
--  $Id: i2c_master_bit_ctrl.vhd,v 1.3 2002-10-30 18:09:53 rherveille Exp $
--  $Id: i2c_master_bit_ctrl.vhd,v 1.4 2002-11-30 22:24:37 rherveille Exp $
--
--
--  $Date: 2002-10-30 18:09:53 $
--  $Date: 2002-11-30 22:24:37 $
--  $Revision: 1.3 $
--  $Revision: 1.4 $
--  $Author: rherveille $
--  $Author: rherveille $
--  $Locker:  $
--  $Locker:  $
--  $State: Exp $
--  $State: Exp $
--
--
-- Change History:
-- Change History:
--               $Log: not supported by cvs2svn $
--               $Log: not supported by cvs2svn $
 
--               Revision 1.3  2002/10/30 18:09:53  rherveille
 
--               Fixed some reported minor start/stop generation timing issuess.
 
--
--               Revision 1.2  2002/06/15 07:37:04  rherveille
--               Revision 1.2  2002/06/15 07:37:04  rherveille
--               Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
--               Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
--
--
--               Revision 1.1  2001/11/05 12:02:33  rherveille
--               Revision 1.1  2001/11/05 12:02:33  rherveille
--               Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
--               Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
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library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
 
 
entity i2c_master_bit_ctrl is
entity i2c_master_bit_ctrl is
        generic(
 
                Tcq : time := 1 ns
 
        );
 
        port (
        port (
                clk    : in std_logic;
                clk    : in std_logic;
                rst    : in std_logic;
                rst    : in std_logic;
                nReset : in std_logic;
                nReset : in std_logic;
                ena    : in std_logic;                          -- core enable signal
                ena    : in std_logic;                          -- core enable signal
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begin
begin
        -- synchronize SCL and SDA inputs
        -- synchronize SCL and SDA inputs
        synch_scl_sda: process(clk)
        synch_scl_sda: process(clk)
        begin
        begin
            if (clk'event and clk = '1') then
            if (clk'event and clk = '1') then
              sSCL <= scl_i after Tcq;
              sSCL <= scl_i;
              sSDA <= sda_i after Tcq;
              sSDA <= sda_i;
            end if;
            end if;
        end process synch_SCL_SDA;
        end process synch_SCL_SDA;
 
 
        -- delay scl_oen
        -- delay scl_oen
        process (clk)
        process (clk)
        begin
        begin
            if (clk'event and clk = '1') then
            if (clk'event and clk = '1') then
              dscl_oen <= iscl_oen after Tcq;
              dscl_oen <= iscl_oen;
            end if;
            end if;
        end process;
        end process;
 
 
        -- whenever the slave is not ready it can delay the cycle by pulling SCL low
        -- whenever the slave is not ready it can delay the cycle by pulling SCL low
        slave_wait <= dscl_oen and not sSCL;
        slave_wait <= dscl_oen and not sSCL;
 
 
        -- generate clk enable signal
        -- generate clk enable signal
        gen_clken: process(clk, nReset)
        gen_clken: process(clk, nReset)
        begin
        begin
            if (nReset = '0') then
            if (nReset = '0') then
              cnt    <= (others => '0') after Tcq;
              cnt    <= (others => '0');
              clk_en <= '1' after Tcq;
              clk_en <= '1';
            elsif (clk'event and clk = '1') then
            elsif (clk'event and clk = '1') then
              if (rst = '1') then
              if (rst = '1') then
                cnt    <= (others => '0') after Tcq;
                cnt    <= (others => '0');
                clk_en <= '1' after Tcq;
                clk_en <= '1';
              else
              else
                if ( (cnt = 0) or (ena = '0') ) then
                if ( (cnt = 0) or (ena = '0') ) then
                  clk_en <= '1' after Tcq;
                  clk_en <= '1';
                  cnt    <= clk_cnt after Tcq;
                  cnt    <= clk_cnt;
                else
                else
                  if (slave_wait = '0') then
                  if (slave_wait = '0') then
                    cnt <= cnt -1 after Tcq;
                    cnt <= cnt -1;
                  end if;
                  end if;
                  clk_en <= '0' after Tcq;
                  clk_en <= '0';
                end if;
                end if;
              end if;
              end if;
            end if;
            end if;
        end process gen_clken;
        end process gen_clken;
 
 
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            -- generate bus busy signal
            -- generate bus busy signal
            gen_busy: process(clk, nReset)
            gen_busy: process(clk, nReset)
            begin
            begin
                if (nReset = '0') then
                if (nReset = '0') then
                  ibusy <= '0' after Tcq;
                  ibusy <= '0';
                elsif (clk'event and clk = '1') then
                elsif (clk'event and clk = '1') then
                  if (rst = '1') then
                  if (rst = '1') then
                    ibusy <= '0' after Tcq;
                    ibusy <= '0';
                  else
                  else
                    ibusy <= (sta_condition or ibusy) and not sto_condition after Tcq;
                    ibusy <= (sta_condition or ibusy) and not sto_condition;
                  end if;
                  end if;
                end if;
                end if;
            end process gen_busy;
            end process gen_busy;
 
 
            -- assign output
            -- assign output
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        end block bus_status_ctrl;
        end block bus_status_ctrl;
 
 
 
 
        -- generate statemachine
        -- generate statemachine
        nxt_state_decoder : process (clk, nReset, c_state, cmd)
        nxt_state_decoder : process (clk, nReset, c_state, cmd)
          variable nxt_state : states;
 
          variable icmd_ack, store_sda : std_logic;
 
        begin
        begin
            nxt_state := c_state;
            if (nReset = '0') then
 
              c_state  <= idle;
            icmd_ack := '0'; -- default no acknowledge
              cmd_ack  <= '0';
 
              dout     <= '0';
            store_sda := '0';
              iscl_oen <= '1';
 
              isda_oen <= '1';
 
            elsif (clk'event and clk = '1') then
 
              if (rst = '1') then
 
                c_state  <= idle;
 
                cmd_ack  <= '0';
 
                dout     <= '0';
 
                iscl_oen <= '1';
 
                isda_oen <= '1';
 
              else
 
                cmd_ack <= '0'; -- default no acknowledge
 
 
 
                if (clk_en = '1') then
            case (c_state) is
            case (c_state) is
              -- idle
              -- idle
              when idle =>
              when idle =>
                case cmd is
                case cmd is
                  when I2C_CMD_START =>
                          when I2C_CMD_START => c_state <= start_a;
                    nxt_state := start_a;
                          when I2C_CMD_STOP  => c_state <= stop_a;
 
                          when I2C_CMD_WRITE => c_state <= wr_a;
                  when I2C_CMD_STOP =>
                          when I2C_CMD_READ  => c_state <= rd_a;
                    nxt_state := stop_a;
                          when others        => c_state <= idle; -- NOP command
 
 
                  when I2C_CMD_WRITE =>
 
                    nxt_state := wr_a;
 
 
 
                  when I2C_CMD_READ =>
 
                    nxt_state := rd_a;
 
 
 
                  when others =>  -- NOP command
 
                    nxt_state := idle;
 
                end case;
                end case;
 
 
 
                        iscl_oen <= iscl_oen; -- keep SCL in same state
 
                        isda_oen <= isda_oen; -- keep SDA in same state
 
 
              -- start
              -- start
              when start_a =>
              when start_a =>
                nxt_state := start_b;
                        c_state  <= start_b;
 
                        iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)
 
                        isda_oen <= '1';      -- set SDA high
 
 
              when start_b =>
              when start_b =>
                nxt_state := start_c;
                        c_state  <= start_c;
 
                        iscl_oen <= '1'; -- set SCL high
 
                        isda_oen <= '1'; -- keep SDA high
 
 
              when start_c =>
              when start_c =>
                nxt_state := start_d;
                        c_state  <= start_d;
 
                        iscl_oen <= '1'; -- keep SCL high
 
                        isda_oen <= '0'; -- set SDA low
 
 
              when start_d =>
              when start_d =>
                nxt_state := start_e;
                        c_state  <= start_e;
 
                        iscl_oen <= '1'; -- keep SCL high
 
                        isda_oen <= '0'; -- keep SDA low
 
 
              when start_e =>
              when start_e =>
                nxt_state := idle;
                        c_state  <= idle;
                icmd_ack := '1'; -- command completed
                        cmd_ack  <= '1'; -- command completed
 
                        iscl_oen <= '0'; -- set SCL low
 
                        isda_oen <= '0'; -- keep SDA low
 
 
              -- stop
              -- stop
              when stop_a =>
              when stop_a =>
                nxt_state := stop_b;
                        c_state  <= stop_b;
 
                        iscl_oen <= '0'; -- keep SCL disabled
 
                        isda_oen <= '0'; -- set SDA low
 
 
              when stop_b =>
              when stop_b =>
                nxt_state := stop_c;
                        c_state  <= stop_c;
 
                        iscl_oen <= '1'; -- set SCL high
 
                        isda_oen <= '0'; -- keep SDA low
 
 
              when stop_c =>
              when stop_c =>
                nxt_state := stop_d;
                        c_state  <= stop_d;
 
                        iscl_oen <= '1'; -- keep SCL high
 
                        isda_oen <= '0'; -- keep SDA low
 
 
              when stop_d =>
              when stop_d =>
                nxt_state := idle;
                        c_state  <= idle;
                icmd_ack := '1'; -- command completed
                        cmd_ack  <= '1'; -- command completed
 
                        iscl_oen <= '1'; -- keep SCL high
 
                        isda_oen <= '1'; -- set SDA high
 
 
              -- read
              -- read
              when rd_a =>
              when rd_a =>
                nxt_state := rd_b;
                        c_state  <= rd_b;
 
                        iscl_oen <= '0'; -- keep SCL low
 
                        isda_oen <= '1'; -- tri-state SDA
 
 
              when rd_b =>
              when rd_b =>
                nxt_state := rd_c;
                        c_state  <= rd_c;
 
                        iscl_oen <= '1'; -- set SCL high
 
                        isda_oen <= '1'; -- tri-state SDA
 
 
              when rd_c =>
              when rd_c =>
                nxt_state := rd_d;
                        c_state  <= rd_d;
                store_sda := '1';
                        dout     <= sSDA;
 
                        iscl_oen <= '1'; -- keep SCL high
 
                        isda_oen <= '1'; -- tri-state SDA
 
 
              when rd_d =>
              when rd_d =>
                nxt_state := idle;
                        c_state  <= idle;
                icmd_ack := '1'; -- command completed
                        cmd_ack  <= '1'; -- command completed
 
                        iscl_oen <= '0'; -- set SCL low
 
                        isda_oen <= '1'; -- tri-state SDA
 
 
              -- write
              -- write
              when wr_a =>
              when wr_a =>
                nxt_state := wr_b;
                        c_state  <= wr_b;
 
                        iscl_oen <= '0'; -- keep SCL low
 
                        isda_oen <= din; -- set SDA
 
 
              when wr_b =>
              when wr_b =>
                nxt_state := wr_c;
                        c_state  <= wr_c;
 
                        iscl_oen <= '1'; -- set SCL high
 
                        isda_oen <= din; -- keep SDA
 
 
              when wr_c =>
              when wr_c =>
                nxt_state := wr_d;
                        c_state  <= wr_d;
 
                        iscl_oen <= '1'; -- keep SCL high
 
                        isda_oen <= din; -- keep SDA
 
 
              when wr_d =>
              when wr_d =>
                nxt_state := idle;
                        c_state  <= idle;
                icmd_ack := '1'; -- command completed
                        cmd_ack  <= '1'; -- command completed
 
                        iscl_oen <= '0'; -- set SCL low
 
                        isda_oen <= din; -- keep SDA
 
 
            end case;
                     when others =>
 
 
            -- generate regs
 
            if (nReset = '0') then
 
              c_state <= idle after Tcq;
 
              cmd_ack <= '0' after Tcq;
 
              Dout    <= '0' after Tcq;
 
            elsif (clk'event and clk = '1') then
 
              if (rst = '1') then
 
                c_state <= idle after Tcq;
 
                cmd_ack <= '0' after Tcq;
 
                Dout    <= '0' after Tcq;
 
              elsif (clk_en = '1') then
 
                c_state <= nxt_state after Tcq;
 
 
 
                if (store_sda = '1') then
                  end case;
                  dout <= sSDA after Tcq;
 
                end if;
                end if;
              end if;
              end if;
 
 
              cmd_ack <= icmd_ack and clk_en;
 
            end if;
            end if;
        end process nxt_state_decoder;
        end process nxt_state_decoder;
 
 
        --
 
        -- convert states to SCL and SDA signals
 
        --
 
        output_decoder: process (clk, nReset, c_state, iscl_oen, isda_oen, din)
 
          variable iscl, isda : std_logic;
 
        begin
 
            case (c_state) is
 
              -- idle
 
              when idle =>
 
                iscl := iscl_oen; -- keep SCL in same state
 
                isda := isda_oen; -- keep SDA in same state
 
 
 
              -- start
 
              when start_a =>
 
                iscl := iscl_oen; -- keep SCL in same state (for repeated start)
 
                isda := '1';      -- set SDA high
 
 
 
              when start_b =>
 
                iscl := '1'; -- set SCL high
 
                isda := '1'; -- keep SDA high
 
 
 
              when start_c =>
 
                iscl := '1'; -- keep SCL high
 
                isda := '0'; -- set SDA low
 
 
 
              when start_d =>
 
                iscl := '1'; -- keep SCL high
 
                isda := '0'; -- keep SDA low
 
 
 
              when start_e =>
 
                iscl := '0'; -- set SCL low
 
                isda := '0'; -- keep SDA low
 
 
 
              -- stop
 
              when stop_a =>
 
                iscl := '0'; -- keep SCL disabled
 
                isda := '0'; -- set SDA low
 
 
 
              when stop_b =>
 
                 iscl := '1'; -- set SCL high
 
                 isda := '0'; -- keep SDA low
 
 
 
              when stop_c =>
 
                 iscl := '1'; -- keep SCL high
 
                 isda := '0'; -- keep SDA low
 
 
 
              when stop_d =>
 
                iscl := '1'; -- keep SCL high
 
                isda := '1'; -- set SDA high
 
 
 
              -- write
 
              when wr_a =>
 
                iscl := '0'; -- keep SCL low
 
                isda := din; -- set SDA
 
 
 
              when wr_b =>
 
                iscl := '1'; -- set SCL high
 
                isda := din; -- keep SDA
 
 
 
              when wr_c =>
 
                iscl := '1'; -- keep SCL high
 
                isda := din; -- keep SDA
 
 
 
              when wr_d =>
 
                iscl := '0'; -- set SCL low
 
                isda := din; -- keep SDA
 
 
 
              -- read
 
              when rd_a =>
 
                iscl := '0'; -- keep SCL low
 
                isda := '1'; -- tri-state SDA
 
 
 
              when rd_b =>
 
                iscl := '1'; -- set SCL high
 
                isda := '1'; -- tri-state SDA
 
 
 
              when rd_c =>
 
                iscl := '1'; -- keep SCL high
 
                isda := '1'; -- tri-state SDA
 
 
 
              when rd_d =>
 
                iscl := '0'; -- set SCL low
 
                isda := '1'; -- tri-state SDA
 
            end case;
 
 
 
            -- generate registers
 
            if (nReset = '0') then
 
              iscl_oen <= '1' after Tcq;
 
              isda_oen <= '1' after Tcq;
 
            elsif (clk'event and clk = '1') then
 
              if (rst = '1') then
 
                iscl_oen <= '1' after Tcq;
 
                isda_oen <= '1' after Tcq;
 
              elsif (clk_en = '1') then
 
                iscl_oen <= iscl after Tcq;
 
                isda_oen <= isda after Tcq;
 
              end if;
 
            end if;
 
        end process output_decoder;
 
 
 
        -- assign outputs
        -- assign outputs
        scl_o   <= '0';
        scl_o   <= '0';
        scl_oen <= iscl_oen;
        scl_oen <= iscl_oen;
        sda_o   <= '0';
        sda_o   <= '0';

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