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---- ----
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---- ----
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- CVS Log
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-- CVS Log
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--
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--
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-- $Id: i2c_master_bit_ctrl.vhd,v 1.5 2002-12-26 16:05:47 rherveille Exp $
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-- $Id: i2c_master_bit_ctrl.vhd,v 1.6 2003-02-01 02:03:06 rherveille Exp $
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--
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--
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-- $Date: 2002-12-26 16:05:47 $
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-- $Date: 2003-02-01 02:03:06 $
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-- $Revision: 1.5 $
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-- $Revision: 1.6 $
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-- $Author: rherveille $
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-- $Author: rherveille $
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-- $Locker: $
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-- $Locker: $
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-- $State: Exp $
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-- $State: Exp $
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--
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--
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-- Change History:
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-- Change History:
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.5 2002/12/26 16:05:47 rherveille
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-- Core is now a Multimaster I2C controller.
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--
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-- Revision 1.4 2002/11/30 22:24:37 rherveille
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-- Revision 1.4 2002/11/30 22:24:37 rherveille
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-- Cleaned up code
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-- Cleaned up code
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--
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--
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-- Revision 1.3 2002/10/30 18:09:53 rherveille
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-- Revision 1.3 2002/10/30 18:09:53 rherveille
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-- Fixed some reported minor start/stop generation timing issuess.
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-- Fixed some reported minor start/stop generation timing issuess.
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signal iscl_oen, isda_oen : std_logic; -- internal I2C lines
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signal iscl_oen, isda_oen : std_logic; -- internal I2C lines
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signal sda_chk : std_logic; -- check SDA status (multi-master arbitration)
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signal sda_chk : std_logic; -- check SDA status (multi-master arbitration)
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signal dscl_oen : std_logic; -- delayed scl_oen signals
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signal dscl_oen : std_logic; -- delayed scl_oen signals
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signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs
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signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs
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signal clk_en, slave_wait :std_logic; -- clock generation signals
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signal clk_en, slave_wait :std_logic; -- clock generation signals
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signal ial : std_logic; -- internal arbitration lost signal
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-- signal cnt : unsigned(15 downto 0) := clk_cnt; -- clock divider counter (simulation)
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-- signal cnt : unsigned(15 downto 0) := clk_cnt; -- clock divider counter (simulation)
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signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis)
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signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis)
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begin
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begin
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-- whenever the slave is not ready it can delay the cycle by pulling SCL low
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-- whenever the slave is not ready it can delay the cycle by pulling SCL low
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dcmd_stop <= cmd_stop;
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dcmd_stop <= cmd_stop;
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al <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not dcmd_stop);
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al <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not dcmd_stop);
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end if;
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end if;
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end process gen_al;
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end process gen_al;
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ial <= al;
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-- generate dout signal, store dout on rising edge of SCL
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-- generate dout signal, store dout on rising edge of SCL
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gen_dout: process(clk)
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gen_dout: process(clk)
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begin
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begin
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if (clk'event and clk = '1') then
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if (clk'event and clk = '1') then
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cmd_ack <= '0';
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cmd_ack <= '0';
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iscl_oen <= '1';
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iscl_oen <= '1';
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isda_oen <= '1';
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isda_oen <= '1';
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sda_chk <= '0';
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sda_chk <= '0';
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elsif (clk'event and clk = '1') then
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elsif (clk'event and clk = '1') then
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if (rst = '1') then
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if (rst = '1' or ial = '1') then
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c_state <= idle;
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c_state <= idle;
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cmd_ack <= '0';
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cmd_ack <= '0';
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iscl_oen <= '1';
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iscl_oen <= '1';
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isda_oen <= '1';
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isda_oen <= '1';
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sda_chk <= '0';
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sda_chk <= '0';
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scl_oen <= iscl_oen;
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scl_oen <= iscl_oen;
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sda_o <= '0';
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sda_o <= '0';
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sda_oen <= isda_oen;
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sda_oen <= isda_oen;
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end architecture structural;
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end architecture structural;
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