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---- ----
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---- ----
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- CVS Log
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-- CVS Log
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--
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--
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-- $Id: i2c_master_bit_ctrl.vhd,v 1.14 2006-10-11 12:10:13 rherveille Exp $
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-- $Id: i2c_master_bit_ctrl.vhd,v 1.15 2009-01-20 10:34:51 rherveille Exp $
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--
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--
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-- $Date: 2006-10-11 12:10:13 $
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-- $Date: 2009-01-20 10:34:51 $
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-- $Revision: 1.14 $
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-- $Revision: 1.15 $
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-- $Author: rherveille $
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-- $Author: rherveille $
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-- $Locker: $
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-- $Locker: $
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-- $State: Exp $
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-- $State: Exp $
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--
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--
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-- Change History:
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-- Change History:
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.14 2006/10/11 12:10:13 rherveille
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-- Added missing semicolons ';' on endif
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--
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-- Revision 1.13 2006/10/06 10:48:24 rherveille
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-- Revision 1.13 2006/10/06 10:48:24 rherveille
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-- fixed short scl high pulse after clock stretch
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-- fixed short scl high pulse after clock stretch
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--
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--
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-- Revision 1.12 2004/05/07 11:53:31 rherveille
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-- Revision 1.12 2004/05/07 11:53:31 rherveille
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-- Fixed previous fix :) Made a variable vs signal mistake.
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-- Fixed previous fix :) Made a variable vs signal mistake.
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signal iscl_oen, isda_oen : std_logic; -- internal I2C lines
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signal iscl_oen, isda_oen : std_logic; -- internal I2C lines
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signal sda_chk : std_logic; -- check SDA status (multi-master arbitration)
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signal sda_chk : std_logic; -- check SDA status (multi-master arbitration)
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signal dscl_oen : std_logic; -- delayed scl_oen signals
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signal dscl_oen : std_logic; -- delayed scl_oen signals
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signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs
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signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs
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signal clk_en, slave_wait : std_logic; -- clock generation signals
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signal dSCL, dSDA : std_logic; -- delayed versions ofsSCL and sSDA
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signal clk_en : std_logic; -- statemachine clock enable
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signal scl_sync, slave_wait : std_logic; -- clock generation signals
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signal ial : std_logic; -- internal arbitration lost signal
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signal ial : std_logic; -- internal arbitration lost signal
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-- signal cnt : unsigned(15 downto 0) := clk_cnt; -- clock divider counter (simulation)
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-- signal cnt : unsigned(15 downto 0) := clk_cnt; -- clock divider counter (simulation)
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signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis)
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signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis)
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begin
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begin
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begin
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begin
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if (clk'event and clk = '1') then
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if (clk'event and clk = '1') then
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dscl_oen <= iscl_oen;
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dscl_oen <= iscl_oen;
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end if;
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end if;
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end process;
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end process;
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slave_wait <= dscl_oen and not sSCL;
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-- slave_wait is asserted when master wants to drive SCL high, but the slave (another master) pulls it low
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-- slave_wait remains asserted until the slave (other master) releases SCL
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process (clk, nReset)
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begin
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if (nReset = '0') then
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slave_wait <= '0';
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else
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slave_wait <= (scl_oen and not dscl_oen and not sSCL) or (slave_wait and not sSCL);
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end if;
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end process;
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-- master drives SCL high, but another master pulls it low
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-- master start counting down its low cycle now (clock synchronization)
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scl_sync <= dSCL and not sSCL and scl_oen;
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-- generate clk enable signal
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-- generate clk enable signal
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gen_clken: process(clk, nReset)
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gen_clken: process(clk, nReset)
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begin
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begin
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if (nReset = '0') then
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if (nReset = '0') then
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clk_en <= '1';
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clk_en <= '1';
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elsif (clk'event and clk = '1') then
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elsif (clk'event and clk = '1') then
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if (rst = '1') then
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if (rst = '1') then
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cnt <= (others => '0');
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cnt <= (others => '0');
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clk_en <= '1';
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clk_en <= '1';
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elsif ( (cnt = 0) or (ena = '0') ) then
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elsif ( (cnt = 0) or (ena = '0') or (scl_sync = '1') ) then
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cnt <= clk_cnt;
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cnt <= clk_cnt;
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clk_en <= '1';
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clk_en <= '1';
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elsif (slave_wait = '1') then
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elsif (slave_wait = '1') then
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cnt <= cnt;
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cnt <= cnt;
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clk_en <= '0';
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clk_en <= '0';
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end process gen_clken;
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end process gen_clken;
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-- generate bus status controller
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-- generate bus status controller
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bus_status_ctrl: block
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bus_status_ctrl: block
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signal dSCL, dSDA : std_logic; -- delayes sSCL and sSDA
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signal sta_condition : std_logic; -- start detected
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signal sta_condition : std_logic; -- start detected
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signal sto_condition : std_logic; -- stop detected
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signal sto_condition : std_logic; -- stop detected
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signal cmd_stop : std_logic; -- STOP command
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signal cmd_stop : std_logic; -- STOP command
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signal ibusy : std_logic; -- internal busy signal
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signal ibusy : std_logic; -- internal busy signal
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begin
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begin
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