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[/] [i2c/] [trunk/] [rtl/] [vhdl/] [i2c_master_top.vhd] - Diff between revs 68 and 71

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Rev 68 Rev 71
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--  $Author: rherveille $
--  $Author: rherveille $
--  $Locker:  $
--  $Locker:  $
--  $State: Exp $
--  $State: Exp $
--
--
-- Change History:
-- Change History:
--               $Log: not supported by cvs2svn $
 
--               Revision 1.7  2004/03/14 10:17:03  rherveille
--               Revision 1.7  2004/03/14 10:17:03  rherveille
--               Fixed simulation issue when writing to CR register
--               Fixed simulation issue when writing to CR register
--
--
--               Revision 1.6  2003/08/09 07:01:13  rherveille
--               Revision 1.6  2003/08/09 07:01:13  rherveille
--               Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
--               Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
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--
--
 
 
 
 
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
 
 
entity i2c_master_top is
entity i2c_master_top is
        generic(
        generic(
                ARST_LVL : std_logic := '0'                   -- asynchronous reset level
                ARST_LVL : std_logic := '0'                   -- asynchronous reset level
        );
        );
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              iack_o <= wb_cyc_i and wb_stb_i and not iack_o;         -- because timing is always honored
              iack_o <= wb_cyc_i and wb_stb_i and not iack_o;         -- because timing is always honored
            end if;
            end if;
        end process gen_ack_o;
        end process gen_ack_o;
        wb_ack_o <= iack_o;
        wb_ack_o <= iack_o;
 
 
 
 
        -- generate wishbone write access signal
        -- generate wishbone write access signal
        wb_wacc <= wb_cyc_i and wb_stb_i and wb_we_i;
    wb_wacc <= wb_we_i and iack_o;
 
 
        -- assign wb_dat_o
        -- assign wb_dat_o
        assign_dato : process(wb_clk_i)
        assign_dato : process(wb_clk_i)
        begin
        begin
            if (wb_clk_i'event and wb_clk_i = '1') then
            if (wb_clk_i'event and wb_clk_i = '1') then
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        -- decode control register
        -- decode control register
        core_en <= ctr(7);
        core_en <= ctr(7);
        ien     <= ctr(6);
        ien     <= ctr(6);
 
 
        -- hookup byte controller block
        -- hookup byte controller block
        byte_ctrl: i2c_master_byte_ctrl port map (
    byte_ctrl: i2c_master_byte_ctrl
 
    port map (
                clk      => wb_clk_i,
                clk      => wb_clk_i,
                rst      => wb_rst_i,
                rst      => wb_rst_i,
                nReset   => rst_i,
                nReset   => rst_i,
                ena      => core_en,
                ena      => core_en,
                clk_cnt  => prer,
                clk_cnt  => prer,

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