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[/] [light8080/] [trunk/] [verilog/] [syn/] [xilinx_s3/] [l80soc_summary.html] - Diff between revs 88 and 90

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`<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>`	`<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>`
`<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>`	`<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>`
`<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>`	`<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>`
`<TR ALIGN=CENTER BGCOLOR='#99CCFF'>`	`<TR ALIGN=CENTER BGCOLOR='#99CCFF'>`
`<TD ALIGN=CENTER COLSPAN='4'><B>l80soc Project Status (04/28/2012 - 12:00:22)</B></TD></TR>`	`<TD ALIGN=CENTER COLSPAN='4'><B>l80soc Project Status (04/29/2012 - 17:48:33)</B></TD></TR>`
`<TR ALIGN=LEFT>`	`<TR ALIGN=LEFT>`
`<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>`	`<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>`
`<TD>xilinx_s3.xise</TD>`	`<TD>xilinx_s3.xise</TD>`
`<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>`	`<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>`
`<TD> No Errors </TD>`	`<TD> No Errors </TD>`
Line 15...	Line 15...
`<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>`	`<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>`
`<TD>Placed and Routed</TD>`	`<TD>Placed and Routed</TD>`
`</TR>`	`</TR>`
`<TR ALIGN=LEFT>`	`<TR ALIGN=LEFT>`
`<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>`	`<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>`
`<TD>xc3s200-4ft256</TD>`	`<TD>xc6slx9-3tqg144</TD>`
`<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>`	`<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>`
`<TD>`	`<TD>`
`No Errors</TD>`	`No Errors</TD>`
`</TR>`	`</TR>`
`<TR ALIGN=LEFT>`	`<TR ALIGN=LEFT>`
`<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.4</TD>`	`<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.4</TD>`
`<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>`	`<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>`
`<TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/*.xmsgs?&DataKey=Warning'>22 Warnings (0 new)</A></TD>`	`<TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/*.xmsgs?&DataKey=Warning'>16 Warnings (7 new)</A></TD>`
`</TR>`	`</TR>`
`<TR ALIGN=LEFT>`	`<TR ALIGN=LEFT>`
`<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>`	`<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>`
`<TD>Balanced</TD>`	`<TD>Balanced</TD>`
`<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>`	`<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>`
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` <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>`	` <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>`
`<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR>`	`<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR>`
`<TR ALIGN=CENTER BGCOLOR='#FFFF99'>`	`<TR ALIGN=CENTER BGCOLOR='#FFFF99'>`
`<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>`	`<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>`
`</TR>`	`</TR>`
`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Flip Flops</TD>`	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>`
`<TD ALIGN=RIGHT>237</TD>`	`<TD ALIGN=RIGHT>229</TD>`
`<TD ALIGN=RIGHT>3,840</TD>`	`<TD ALIGN=RIGHT>11,440</TD>`
`<TD ALIGN=RIGHT>6%</TD>`	`<TD ALIGN=RIGHT>2%</TD>`
`<TD COLSPAN='2'> </TD>`	`<TD COLSPAN='2'> </TD>`
`</TR>`	`</TR>`
`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of 4 input LUTs</TD>`	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as Flip Flops</TD>`
`<TD ALIGN=RIGHT>384</TD>`	`<TD ALIGN=RIGHT>229</TD>`
`<TD ALIGN=RIGHT>3,840</TD>`	`<TD> </TD>`
`<TD ALIGN=RIGHT>10%</TD>`	`<TD> </TD>`
`<TD COLSPAN='2'> </TD>`	`<TD COLSPAN='2'> </TD>`
`</TR>`	`</TR>`
`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>`	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as Latches</TD>`
`<TD ALIGN=RIGHT>255</TD>`	`<TD ALIGN=RIGHT>0</TD>`
`<TD ALIGN=RIGHT>1,920</TD>`	`<TD> </TD>`
`<TD ALIGN=RIGHT>13%</TD>`	`<TD> </TD>`
`<TD COLSPAN='2'> </TD>`	`<TD COLSPAN='2'> </TD>`
`</TR>`	`</TR>`
`<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number of Slices containing only related logic</TD>`	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as Latch-thrus</TD>`
`<TD ALIGN=RIGHT>255</TD>`	`<TD ALIGN=RIGHT>0</TD>`
`<TD ALIGN=RIGHT>255</TD>`	`<TD> </TD>`
`<TD ALIGN=RIGHT>100%</TD>`	`<TD> </TD>`
`<TD COLSPAN='2'> </TD>`	`<TD COLSPAN='2'> </TD>`
`</TR>`	`</TR>`
`<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number of Slices containing unrelated logic</TD>`	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as AND/OR logics</TD>`
`<TD ALIGN=RIGHT>0</TD>`	`<TD ALIGN=RIGHT>0</TD>`
`<TD ALIGN=RIGHT>255</TD>`	`<TD> </TD>`
`<TD ALIGN=RIGHT>0%</TD>`	`<TD> </TD>`
`<TD COLSPAN='2'> </TD>`	`<TD COLSPAN='2'> </TD>`
`</TR>`	`</TR>`
`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Total Number of 4 input LUTs</TD>`	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>`
`<TD ALIGN=RIGHT>385</TD>`	`<TD ALIGN=RIGHT>278</TD>`
`<TD ALIGN=RIGHT>3,840</TD>`	`<TD ALIGN=RIGHT>5,720</TD>`
`<TD ALIGN=RIGHT>10%</TD>`	`<TD ALIGN=RIGHT>4%</TD>`
`<TD COLSPAN='2'> </TD>`	`<TD COLSPAN='2'> </TD>`
`</TR>`	`</TR>`
`<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as logic</TD>`	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as logic</TD>`
`<TD ALIGN=RIGHT>368</TD>`	`<TD ALIGN=RIGHT>269</TD>`
	`<TD ALIGN=RIGHT>5,720</TD>`
	`<TD ALIGN=RIGHT>4%</TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number using O6 output only</TD>`
	`<TD ALIGN=RIGHT>220</TD>`
	`<TD> </TD>`
	`<TD> </TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number using O5 output only</TD>`
	`<TD ALIGN=RIGHT>0</TD>`
	`<TD> </TD>`
	`<TD> </TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number using O5 and O6</TD>`
	`<TD ALIGN=RIGHT>49</TD>`
	`<TD> </TD>`
	`<TD> </TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number used as ROM</TD>`
	`<TD ALIGN=RIGHT>0</TD>`
	`<TD> </TD>`
	`<TD> </TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as Memory</TD>`
	`<TD ALIGN=RIGHT>8</TD>`
	`<TD ALIGN=RIGHT>1,440</TD>`
	`<TD ALIGN=RIGHT>1%</TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number used as Dual Port RAM</TD>`
	`<TD ALIGN=RIGHT>8</TD>`
	`<TD> </TD>`
	`<TD> </TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>            Number using O6 output only</TD>`
	`<TD ALIGN=RIGHT>4</TD>`
	`<TD> </TD>`
	`<TD> </TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>            Number using O5 output only</TD>`
	`<TD ALIGN=RIGHT>0</TD>`
	`<TD> </TD>`
	`<TD> </TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>            Number using O5 and O6</TD>`
	`<TD ALIGN=RIGHT>4</TD>`
	`<TD> </TD>`
	`<TD> </TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number used as Single Port RAM</TD>`
	`<TD ALIGN=RIGHT>0</TD>`
	`<TD> </TD>`
	`<TD> </TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number used as Shift Register</TD>`
	`<TD ALIGN=RIGHT>0</TD>`
`<TD> </TD>`	`<TD> </TD>`
`<TD> </TD>`	`<TD> </TD>`
`<TD COLSPAN='2'> </TD>`	`<TD COLSPAN='2'> </TD>`
`</TR>`	`</TR>`
`<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as a route-thru</TD>`	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used exclusively as route-thrus</TD>`
`<TD ALIGN=RIGHT>1</TD>`	`<TD ALIGN=RIGHT>1</TD>`
`<TD> </TD>`	`<TD> </TD>`
`<TD> </TD>`	`<TD> </TD>`
`<TD COLSPAN='2'> </TD>`	`<TD COLSPAN='2'> </TD>`
`</TR>`	`</TR>`
`<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used for Dual Port RAMs</TD>`	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number with same-slice register load</TD>`
`<TD ALIGN=RIGHT>16</TD>`	`<TD ALIGN=RIGHT>0</TD>`
	`<TD> </TD>`
	`<TD> </TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number with same-slice carry load</TD>`
	`<TD ALIGN=RIGHT>1</TD>`
	`<TD> </TD>`
`<TD> </TD>`	`<TD> </TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number with other load</TD>`
	`<TD ALIGN=RIGHT>0</TD>`
`<TD> </TD>`	`<TD> </TD>`
	`<TD> </TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>`
	`<TD ALIGN=RIGHT>106</TD>`
	`<TD ALIGN=RIGHT>1,430</TD>`
	`<TD ALIGN=RIGHT>7%</TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Nummber of MUXCYs used</TD>`
	`<TD ALIGN=RIGHT>36</TD>`
	`<TD ALIGN=RIGHT>2,860</TD>`
	`<TD ALIGN=RIGHT>1%</TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>`
	`<TD ALIGN=RIGHT>336</TD>`
	`<TD> </TD>`
	`<TD> </TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number with an unused Flip Flop</TD>`
	`<TD ALIGN=RIGHT>122</TD>`
	`<TD ALIGN=RIGHT>336</TD>`
	`<TD ALIGN=RIGHT>36%</TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number with an unused LUT</TD>`
	`<TD ALIGN=RIGHT>58</TD>`
	`<TD ALIGN=RIGHT>336</TD>`
	`<TD ALIGN=RIGHT>17%</TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number of fully used LUT-FF pairs</TD>`
	`<TD ALIGN=RIGHT>156</TD>`
	`<TD ALIGN=RIGHT>336</TD>`
	`<TD ALIGN=RIGHT>46%</TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number of unique control sets</TD>`
	`<TD ALIGN=RIGHT>24</TD>`
	`<TD> </TD>`
	`<TD> </TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number of slice register sites lost<BR>        to control set restrictions</TD>`
	`<TD ALIGN=RIGHT>39</TD>`
	`<TD ALIGN=RIGHT>11,440</TD>`
	`<TD ALIGN=RIGHT>1%</TD>`
`<TD COLSPAN='2'> </TD>`	`<TD COLSPAN='2'> </TD>`
`</TR>`	`</TR>`
`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>`	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>`
`<TD ALIGN=RIGHT>24</TD>`	`<TD ALIGN=RIGHT>24</TD>`
`<TD ALIGN=RIGHT>173</TD>`	`<TD ALIGN=RIGHT>102</TD>`
`<TD ALIGN=RIGHT>13%</TD>`	`<TD ALIGN=RIGHT>23%</TD>`
`<TD COLSPAN='2'> </TD>`	`<TD COLSPAN='2'> </TD>`
`</TR>`	`</TR>`
`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16s</TD>`	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16BWERs</TD>`
`<TD ALIGN=RIGHT>3</TD>`	`<TD ALIGN=RIGHT>3</TD>`
`<TD ALIGN=RIGHT>12</TD>`	`<TD ALIGN=RIGHT>32</TD>`
`<TD ALIGN=RIGHT>25%</TD>`	`<TD ALIGN=RIGHT>9%</TD>`
`<TD COLSPAN='2'> </TD>`	`<TD COLSPAN='2'> </TD>`
`</TR>`	`</TR>`
`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFGMUXs</TD>`	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD>`
	`<TD ALIGN=RIGHT>0</TD>`
	`<TD ALIGN=RIGHT>64</TD>`
	`<TD ALIGN=RIGHT>0%</TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2/BUFIO2_2CLKs</TD>`
	`<TD ALIGN=RIGHT>0</TD>`
	`<TD ALIGN=RIGHT>32</TD>`
	`<TD ALIGN=RIGHT>0%</TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2FB/BUFIO2FB_2CLKs</TD>`
	`<TD ALIGN=RIGHT>0</TD>`
	`<TD ALIGN=RIGHT>32</TD>`
	`<TD ALIGN=RIGHT>0%</TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD>`
`<TD ALIGN=RIGHT>1</TD>`	`<TD ALIGN=RIGHT>1</TD>`
	`<TD ALIGN=RIGHT>16</TD>`
	`<TD ALIGN=RIGHT>6%</TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as BUFGs</TD>`
	`<TD ALIGN=RIGHT>1</TD>`
	`<TD> </TD>`
	`<TD> </TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as BUFGMUX</TD>`
	`<TD ALIGN=RIGHT>0</TD>`
	`<TD> </TD>`
	`<TD> </TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCM/DCM_CLKGENs</TD>`
	`<TD ALIGN=RIGHT>0</TD>`
	`<TD ALIGN=RIGHT>4</TD>`
	`<TD ALIGN=RIGHT>0%</TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ILOGIC2/ISERDES2s</TD>`
	`<TD ALIGN=RIGHT>0</TD>`
	`<TD ALIGN=RIGHT>200</TD>`
	`<TD ALIGN=RIGHT>0%</TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IODELAY2/IODRP2/IODRP2_MCBs</TD>`
	`<TD ALIGN=RIGHT>0</TD>`
	`<TD ALIGN=RIGHT>200</TD>`
	`<TD ALIGN=RIGHT>0%</TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of OLOGIC2/OSERDES2s</TD>`
	`<TD ALIGN=RIGHT>0</TD>`
	`<TD ALIGN=RIGHT>200</TD>`
	`<TD ALIGN=RIGHT>0%</TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BSCANs</TD>`
	`<TD ALIGN=RIGHT>0</TD>`
	`<TD ALIGN=RIGHT>4</TD>`
	`<TD ALIGN=RIGHT>0%</TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFHs</TD>`
	`<TD ALIGN=RIGHT>0</TD>`
	`<TD ALIGN=RIGHT>128</TD>`
	`<TD ALIGN=RIGHT>0%</TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLLs</TD>`
	`<TD ALIGN=RIGHT>0</TD>`
`<TD ALIGN=RIGHT>8</TD>`	`<TD ALIGN=RIGHT>8</TD>`
`<TD ALIGN=RIGHT>12%</TD>`	`<TD ALIGN=RIGHT>0%</TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLL_MCBs</TD>`
	`<TD ALIGN=RIGHT>0</TD>`
	`<TD ALIGN=RIGHT>4</TD>`
	`<TD ALIGN=RIGHT>0%</TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DSP48A1s</TD>`
	`<TD ALIGN=RIGHT>0</TD>`
	`<TD ALIGN=RIGHT>16</TD>`
	`<TD ALIGN=RIGHT>0%</TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ICAPs</TD>`
	`<TD ALIGN=RIGHT>0</TD>`
	`<TD ALIGN=RIGHT>1</TD>`
	`<TD ALIGN=RIGHT>0%</TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MCBs</TD>`
	`<TD ALIGN=RIGHT>0</TD>`
	`<TD ALIGN=RIGHT>2</TD>`
	`<TD ALIGN=RIGHT>0%</TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCILOGICSEs</TD>`
	`<TD ALIGN=RIGHT>0</TD>`
	`<TD ALIGN=RIGHT>2</TD>`
	`<TD ALIGN=RIGHT>0%</TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PLL_ADVs</TD>`
	`<TD ALIGN=RIGHT>0</TD>`
	`<TD ALIGN=RIGHT>2</TD>`
	`<TD ALIGN=RIGHT>0%</TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PMVs</TD>`
	`<TD ALIGN=RIGHT>0</TD>`
	`<TD ALIGN=RIGHT>1</TD>`
	`<TD ALIGN=RIGHT>0%</TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of STARTUPs</TD>`
	`<TD ALIGN=RIGHT>0</TD>`
	`<TD ALIGN=RIGHT>1</TD>`
	`<TD ALIGN=RIGHT>0%</TD>`
	`<TD COLSPAN='2'> </TD>`
	`</TR>`
	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of SUSPEND_SYNCs</TD>`
	`<TD ALIGN=RIGHT>0</TD>`
	`<TD ALIGN=RIGHT>1</TD>`
	`<TD ALIGN=RIGHT>0%</TD>`
`<TD COLSPAN='2'> </TD>`	`<TD COLSPAN='2'> </TD>`
`</TR>`	`</TR>`
`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>`	`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>`
`<TD ALIGN=RIGHT>3.39</TD>`	`<TD ALIGN=RIGHT>3.73</TD>`
`<TD> </TD>`	`<TD> </TD>`
`<TD> </TD>`	`<TD> </TD>`
`<TD COLSPAN='2'> </TD>`	`<TD COLSPAN='2'> </TD>`
`</TR>`	`</TR>`
`</TABLE>`	`</TABLE>`
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` <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>`	` <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>`
`<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>`	`<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>`
`<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>`	`<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>`
`<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>`	`<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>`
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sat 28. Apr 11:59:08 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/xst.xmsgs?&DataKey=Warning'>22 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/xst.xmsgs?&DataKey=Info'>7 Infos (1 new)</A></TD></TR>	<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sun 29. Apr 17:46:13 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/xst.xmsgs?&DataKey=Warning'>12 Warnings (3 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/xst.xmsgs?&DataKey=Info'>12 Infos (10 new)</A></TD></TR>
`<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.bld'>Translation Report</A></TD><TD>Current</TD><TD>Sat 28. Apr 11:59:29 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>`	`<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.bld'>Translation Report</A></TD><TD>Current</TD><TD>Sun 29. Apr 17:46:39 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>`
`<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Sat 28. Apr 11:59:43 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/map.xmsgs?&DataKey=Info'>4 Infos (0 new)</A></TD></TR>`	<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Sun 29. Apr 17:47:37 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/map.xmsgs?&DataKey=Warning'>1 Warning (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/map.xmsgs?&DataKey=Info'>8 Infos (6 new)</A></TD></TR>
`<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Sat 28. Apr 12:00:08 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>`	`<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Sun 29. Apr 17:48:11 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/par.xmsgs?&DataKey=Warning'>3 Warnings (3 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>`
`<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>`	`<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>`
`<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Sat 28. Apr 12:00:18 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/trce.xmsgs?&DataKey=Info'>5 Infos (0 new)</A></TD></TR>`	`<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Sun 29. Apr 17:48:31 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>`
`<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>`	`<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>`
`</TABLE>`	`</TABLE>`
` <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>`	` <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>`
`<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>`	`<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>`
`<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>`	`<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>`
`</TABLE>`	`</TABLE>`


`<br><center><b>Date Generated:</b> 04/28/2012 - 12:00:22</center>`	`<br><center><b>Date Generated:</b> 04/29/2012 - 17:48:33</center>`
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