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[/] [mblite/] [trunk/] [designs/] [core/] [testbench.vhd] - Diff between revs 2 and 6

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Rev 2 Rev 6
Line 32... Line 32...
    SIGNAL dmem_o : dmem_out_type;
    SIGNAL dmem_o : dmem_out_type;
    SIGNAL imem_o : imem_out_type;
    SIGNAL imem_o : imem_out_type;
    SIGNAL dmem_i : dmem_in_type;
    SIGNAL dmem_i : dmem_in_type;
    SIGNAL imem_i : imem_in_type;
    SIGNAL imem_i : imem_in_type;
 
 
    SIGNAL sys_clk_i : std_ulogic := '0';
    SIGNAL sys_clk_i : std_logic := '0';
    SIGNAL sys_int_i : std_ulogic := '0';
    SIGNAL sys_int_i : std_logic := '0';
    SIGNAL sys_rst_i : std_ulogic := '0';
    SIGNAL sys_rst_i : std_logic := '0';
    SIGNAL sys_ena_i : std_ulogic := '1';
    SIGNAL sys_ena_i : std_logic := '1';
 
 
    CONSTANT std_out_adr : std_ulogic_vector(CFG_DMEM_SIZE - 1 DOWNTO 0) := X"FFFFFFC0";
    CONSTANT std_out_adr : std_logic_vector(CFG_DMEM_SIZE - 1 DOWNTO 0) := X"FFFFFFC0";
    CONSTANT rom_size : integer := 16;
    CONSTANT rom_size : integer := 16;
    CONSTANT ram_size : integer := 16;
    CONSTANT ram_size : integer := 16;
 
 
    SIGNAL mem_enable : std_ulogic;
    SIGNAL mem_enable : std_logic;
    SIGNAL chr_enable : std_ulogic;
    SIGNAL chr_enable : std_logic;
    SIGNAL chr_read : std_ulogic;
    SIGNAL chr_read : std_logic;
    SIGNAL sel_o : std_ulogic_vector(3 DOWNTO 0);
    SIGNAL sel_o : std_logic_vector(3 DOWNTO 0);
    SIGNAL mem_dat : std_ulogic_vector(31 DOWNTO 0);
    SIGNAL mem_dat : std_logic_vector(31 DOWNTO 0);
    SIGNAL chr_dat : std_ulogic_vector(31 DOWNTO 0);
    SIGNAL chr_dat : std_logic_vector(31 DOWNTO 0);
    SIGNAL chr_cnt : integer := 0;
    SIGNAL chr_cnt : integer := 0;
 
 
BEGIN
BEGIN
 
 
    sys_clk_i <= NOT sys_clk_i AFTER 10000 ps;
    sys_clk_i <= NOT sys_clk_i AFTER 10000 ps;
Line 67... Line 67...
    dmem_i.dat_i <= chr_dat WHEN chr_read = '1' ELSE mem_dat;
    dmem_i.dat_i <= chr_dat WHEN chr_read = '1' ELSE mem_dat;
 
 
    -- Character device
    -- Character device
    stdio: PROCESS(sys_clk_i)
    stdio: PROCESS(sys_clk_i)
        VARIABLE s    : line;
        VARIABLE s    : line;
        VARIABLE byte : std_ulogic_vector(7 DOWNTO 0);
        VARIABLE byte : std_logic_vector(7 DOWNTO 0);
        VARIABLE char : character;
        VARIABLE char : character;
    BEGIN
    BEGIN
        IF rising_edge(sys_clk_i) THEN
        IF rising_edge(sys_clk_i) THEN
            IF chr_enable = '1' THEN
            IF chr_enable = '1' THEN
                IF dmem_o.we_o = '1' THEN
                IF dmem_o.we_o = '1' THEN

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