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[/] [mblite/] [trunk/] [designs/] [core_decoder/] [testbench.vhd] - Diff between revs 2 and 6

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Rev 2 Rev 6
Line 28... Line 28...
 
 
    COMPONENT mblite_stdio IS PORT
    COMPONENT mblite_stdio IS PORT
    (
    (
        dmem_i : OUT dmem_in_type;
        dmem_i : OUT dmem_in_type;
        dmem_o : IN dmem_out_type;
        dmem_o : IN dmem_out_type;
        clk_i  : IN std_ulogic
        clk_i  : IN std_logic
    );
    );
    END COMPONENT;
    END COMPONENT;
 
 
    SIGNAL dmem_o : dmem_out_type;
    SIGNAL dmem_o : dmem_out_type;
    SIGNAL dmem_i : dmem_in_type;
    SIGNAL dmem_i : dmem_in_type;
    SIGNAL imem_o : imem_out_type;
    SIGNAL imem_o : imem_out_type;
    SIGNAL imem_i : imem_in_type;
    SIGNAL imem_i : imem_in_type;
    SIGNAL s_dmem_o : dmem_out_array_type(CFG_NUM_SLAVES - 1 DOWNTO 0);
    SIGNAL s_dmem_o : dmem_out_array_type(CFG_NUM_SLAVES - 1 DOWNTO 0);
    SIGNAL s_dmem_i : dmem_in_array_type(CFG_NUM_SLAVES - 1 DOWNTO 0);
    SIGNAL s_dmem_i : dmem_in_array_type(CFG_NUM_SLAVES - 1 DOWNTO 0);
 
 
    SIGNAL sys_clk_i : std_ulogic := '0';
    SIGNAL sys_clk_i : std_logic := '0';
    SIGNAL sys_int_i : std_ulogic;
    SIGNAL sys_int_i : std_logic;
    SIGNAL sys_rst_i : std_ulogic;
    SIGNAL sys_rst_i : std_logic;
 
 
    CONSTANT rom_size : integer := 16;
    CONSTANT rom_size : integer := 16;
    CONSTANT ram_size : integer := 16;
    CONSTANT ram_size : integer := 16;
 
 
    SIGNAL sel_o : std_ulogic_vector(3 DOWNTO 0);
    SIGNAL sel_o : std_logic_vector(3 DOWNTO 0);
    SIGNAL ena_o : std_ulogic;
    SIGNAL ena_o : std_logic;
 
 
BEGIN
BEGIN
 
 
    sys_clk_i <= NOT sys_clk_i AFTER 10000 ps;
    sys_clk_i <= NOT sys_clk_i AFTER 10000 ps;
    sys_rst_i <= '1' AFTER 0 ps, '0' AFTER  150000 ps;
    sys_rst_i <= '1' AFTER 0 ps, '0' AFTER  150000 ps;

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