URL https://opencores.org/ocsvn/mblite/mblite/trunk

Subversion Repositories mblite

[/] [mblite/] [trunk/] [designs/] [core_decoder_wb/] [testbench.vhd] - Diff between revs 2 and 6

Rev 2	Rev 6
Line 43...	Line 43...
`SIGNAL m_wb_i : wb_mst_in_type;`	`SIGNAL m_wb_i : wb_mst_in_type;`
`SIGNAL m_wb_o : wb_mst_out_type;`	`SIGNAL m_wb_o : wb_mst_out_type;`
`SIGNAL s_wb_i : wb_slv_in_type;`	`SIGNAL s_wb_i : wb_slv_in_type;`
`SIGNAL s_wb_o : wb_slv_out_type;`	`SIGNAL s_wb_o : wb_slv_out_type;`

`SIGNAL sys_clk_i : std_ulogic := '0';`	`SIGNAL sys_clk_i : std_logic := '0';`
`SIGNAL sys_int_i : std_ulogic;`	`SIGNAL sys_int_i : std_logic;`
`SIGNAL sys_rst_i : std_ulogic;`	`SIGNAL sys_rst_i : std_logic;`

`CONSTANT rom_size : integer := 16;`	`CONSTANT rom_size : integer := 16;`
`CONSTANT ram_size : integer := 16;`	`CONSTANT ram_size : integer := 16;`

`SIGNAL sel_o : std_ulogic_vector(3 DOWNTO 0);`	`SIGNAL sel_o : std_logic_vector(3 DOWNTO 0);`
`SIGNAL ena_o : std_ulogic;`	`SIGNAL ena_o : std_logic;`

`BEGIN`	`BEGIN`

`sys_clk_i <= NOT sys_clk_i AFTER 10000 ps;`	`sys_clk_i <= NOT sys_clk_i AFTER 10000 ps;`
`sys_rst_i <= '1' AFTER 0 ps, '0' AFTER 150000 ps;`	`sys_rst_i <= '1' AFTER 0 ps, '0' AFTER 150000 ps;`