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[/] [mblite/] [trunk/] [designs/] [core_syn/] [sram_4en_init.vhd] - Diff between revs 6 and 8

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Rev 6 Rev 8
Line 11... Line 11...
--                           ports.
--                           ports.
--                           Initialized with hello world program
--                           Initialized with hello world program
--
--
----------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------
 
 
LIBRARY ieee;
library ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.ALL;
use ieee.std_logic_unsigned.all;
 
 
LIBRARY mblite;
library mblite;
USE mblite.std_Pkg.ALL;
use mblite.std_Pkg.all;
 
 
ENTITY sram_4en_init IS GENERIC
entity sram_4en_init is generic
(
(
    WIDTH : integer := 32;
    WIDTH : integer := 32;
    SIZE  : integer := 11
    SIZE  : integer := 11
);
);
PORT
port
(
(
    dat_o                   : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
    dat_o                   : out std_logic_vector(WIDTH - 1 downto 0);
    dat_i                   : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
    dat_i                   : in std_logic_vector(WIDTH - 1 downto 0);
    adr_i                   : IN std_logic_vector(SIZE - 1 DOWNTO 0);
    adr_i                   : in std_logic_vector(SIZE - 1 downto 0);
    wre_i                   : IN std_logic_vector(3 DOWNTO 0);
    wre_i                   : in std_logic_vector(3 downto 0);
    ena_i                   : IN std_logic;
    ena_i                   : in std_logic;
    clk_i                   : IN std_logic
    clk_i                   : in std_logic
);
);
END sram_4en_init;
end sram_4en_init;
 
 
ARCHITECTURE arch OF sram_4en_init IS
architecture arch of sram_4en_init is
  TYPE ram_type IS array (0 TO 2 ** SIZE - 1) OF std_logic_vector(WIDTH - 1 DOWNTO 0);
  type ram_type is array (0 to 2 ** size - 1) of std_logic_vector(WIDTH - 1 downto 0);
  SIGNAL ram : ram_type := (
  signal ram : ram_type := (
    X"B8080050",X"00000000",X"B8080728",X"00000000",X"B8080738",X"00000000",X"00000000",X"00000000",
    X"B8080050",X"00000000",X"B8080728",X"00000000",X"B8080738",X"00000000",X"00000000",X"00000000",
    X"B8080730",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
    X"B8080730",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
    X"00000000",X"00000000",X"00000000",X"00000000",X"31A01028",X"30400F18",X"B0000000",X"30209038",
    X"00000000",X"00000000",X"00000000",X"00000000",X"31A01028",X"30400F18",X"B0000000",X"30209038",
    X"B9F400C0",X"80000000",X"B9F406E8",X"30A30000",X"B8000000",X"E0601028",X"3021FFE4",X"F9E10000",
    X"B9F400C0",X"80000000",X"B9F406E8",X"30A30000",X"B8000000",X"E0601028",X"3021FFE4",X"F9E10000",
    X"BC030014",X"B8000040",X"F8600F20",X"99FC2000",X"80000000",X"E8600F20",X"E8830000",X"BE24FFEC",
    X"BC030014",X"B8000040",X"F8600F20",X"99FC2000",X"80000000",X"E8600F20",X"E8830000",X"BE24FFEC",
Line 294... Line 294...
    X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
    X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
    X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
    X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
    X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
    X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
    X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000");
    X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000");
 
 
    SIGNAL di0, di1, di2, di3 : std_logic_vector(WIDTH/4 - 1 DOWNTO 0);
    signal di0, di1, di2, di3 : std_logic_vector(WIDTH/4 - 1 downto 0);
BEGIN
begin
    process(wre_i, dat_i, adr_i)
    process(wre_i, dat_i, adr_i)
    begin
    begin
       if wre_i(0) = '1' then
       if wre_i(0) = '1' then
          di0 <= dat_i(WIDTH/4 - 1 DOWNTO 0);
          di0 <= dat_i(WIDTH/4 - 1 downto 0);
       else
       else
          di0 <= ram(my_conv_integer(adr_i))(WIDTH/4 - 1 DOWNTO 0);
          di0 <= ram(my_conv_integer(adr_i))(WIDTH/4 - 1 downto 0);
       end if;
       end if;
 
 
       if wre_i(1) = '1' then
       if wre_i(1) = '1' then
          di1 <= dat_i(WIDTH/2 - 1 DOWNTO WIDTH/4);
          di1 <= dat_i(WIDTH/2 - 1 downto WIDTH/4);
       else
       else
          di1 <= ram(my_conv_integer(adr_i))(WIDTH/2 - 1 DOWNTO WIDTH/4);
          di1 <= ram(my_conv_integer(adr_i))(WIDTH/2 - 1 downto WIDTH/4);
       end if;
       end if;
 
 
       if wre_i(2) = '1' then
       if wre_i(2) = '1' then
          di2 <= dat_i(3*WIDTH/4 - 1 DOWNTO WIDTH/2);
          di2 <= dat_i(3*WIDTH/4 - 1 downto WIDTH/2);
       else
       else
          di2 <= ram(my_conv_integer(adr_i))(3*WIDTH/4 - 1 DOWNTO WIDTH/2);
          di2 <= ram(my_conv_integer(adr_i))(3*WIDTH/4 - 1 downto WIDTH/2);
       end if;
       end if;
 
 
       if wre_i(3) = '1' then
       if wre_i(3) = '1' then
          di3 <= dat_i(WIDTH-1 DOWNTO 3*WIDTH/4);
          di3 <= dat_i(WIDTH-1 downto 3*WIDTH/4);
       else
       else
          di3 <= ram(my_conv_integer(adr_i))(WIDTH-1 DOWNTO 3*WIDTH/4);
          di3 <= ram(my_conv_integer(adr_i))(WIDTH-1 downto 3*WIDTH/4);
       end if;
       end if;
    end process;
    end process;
 
 
    process(clk_i)
    process(clk_i)
    begin
    begin
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             ram(my_conv_integer(adr_i)) <= di3 & di2 & di1 & di0;
             ram(my_conv_integer(adr_i)) <= di3 & di2 & di1 & di0;
          end if;
          end if;
          dat_o <= ram(my_conv_integer(adr_i));
          dat_o <= ram(my_conv_integer(adr_i));
       end if;
       end if;
    end process;
    end process;
END arch;
 
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end arch;
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