| Line 32... |
Line 32... |
SIGNAL imem_i : imem_in_type;
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SIGNAL imem_i : imem_in_type;
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SIGNAL wb_o : wb_mst_out_type;
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SIGNAL wb_o : wb_mst_out_type;
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SIGNAL wb_i : wb_mst_in_type;
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SIGNAL wb_i : wb_mst_in_type;
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SIGNAL sys_clk_i : std_ulogic := '0';
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SIGNAL sys_clk_i : std_logic := '0';
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SIGNAL sys_int_i : std_ulogic;
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SIGNAL sys_int_i : std_logic;
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SIGNAL sys_rst_i : std_ulogic;
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SIGNAL sys_rst_i : std_logic;
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CONSTANT std_out_adr : std_ulogic_vector(CFG_DMEM_SIZE - 1 DOWNTO 0) := X"FFFFFFC0";
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CONSTANT std_out_adr : std_logic_vector(CFG_DMEM_SIZE - 1 DOWNTO 0) := X"FFFFFFC0";
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SIGNAL std_out_ack : std_ulogic;
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SIGNAL std_out_ack : std_logic;
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SIGNAL stdo_ena : std_ulogic;
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SIGNAL stdo_ena : std_logic;
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SIGNAL dmem_ena : std_ulogic;
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SIGNAL dmem_ena : std_logic;
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SIGNAL dmem_dat : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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SIGNAL dmem_dat : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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SIGNAL dmem_sel : std_ulogic_vector(3 DOWNTO 0);
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SIGNAL dmem_sel : std_logic_vector(3 DOWNTO 0);
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CONSTANT rom_size : integer := 16;
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CONSTANT rom_size : integer := 16;
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CONSTANT ram_size : integer := 16;
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CONSTANT ram_size : integer := 16;
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BEGIN
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BEGIN
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| Line 71... |
Line 71... |
END PROCESS;
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END PROCESS;
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-- Character device
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-- Character device
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wb_stdio_slave: PROCESS(sys_clk_i)
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wb_stdio_slave: PROCESS(sys_clk_i)
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VARIABLE s : line;
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VARIABLE s : line;
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VARIABLE byte : std_ulogic_vector(7 DOWNTO 0);
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VARIABLE byte : std_logic_vector(7 DOWNTO 0);
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VARIABLE char : character;
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VARIABLE char : character;
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BEGIN
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BEGIN
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IF rising_edge(sys_clk_i) THEN
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IF rising_edge(sys_clk_i) THEN
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IF (wb_o.stb_o AND wb_o.cyc_o AND compare(wb_o.adr_o, std_out_adr)) = '1' THEN
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IF (wb_o.stb_o AND wb_o.cyc_o AND compare(wb_o.adr_o, std_out_adr)) = '1' THEN
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IF wb_o.we_o = '1' AND std_out_ack = '0' THEN
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IF wb_o.we_o = '1' AND std_out_ack = '0' THEN
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