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[/] [mblite/] [trunk/] [hw/] [core/] [core_address_decoder.vhd] - Diff between revs 6 and 8

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--
--
--      Description        : Wishbone adapter for the MB-Lite microprocessor
--      Description        : Wishbone adapter for the MB-Lite microprocessor
--
--
----------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------
 
 
LIBRARY ieee;
library ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.ALL;
use ieee.std_logic_unsigned.all;
 
 
LIBRARY mblite;
library mblite;
USE mblite.config_Pkg.ALL;
use mblite.config_Pkg.all;
USE mblite.core_Pkg.ALL;
use mblite.core_Pkg.all;
USE mblite.std_Pkg.ALL;
use mblite.std_Pkg.all;
 
 
ENTITY core_address_decoder IS GENERIC
entity core_address_decoder is generic
(
(
    G_NUM_SLAVES : positive := CFG_NUM_SLAVES;
    G_NUM_SLAVES : positive := CFG_NUM_SLAVES;
    G_MEMORY_MAP : memory_map_type := CFG_MEMORY_MAP
    G_MEMORY_MAP : memory_map_type := CFG_MEMORY_MAP
);
);
PORT
port
(
(
    m_dmem_i : OUT dmem_in_type;
    m_dmem_i : out dmem_in_type;
    s_dmem_o : OUT dmem_out_array_type(G_NUM_SLAVES - 1 DOWNTO 0);
    s_dmem_o : out dmem_out_array_type(G_NUM_SLAVES - 1 downto 0);
    m_dmem_o : IN dmem_out_type;
    m_dmem_o : in dmem_out_type;
    s_dmem_i : IN dmem_in_array_type(G_NUM_SLAVES - 1 DOWNTO 0);
    s_dmem_i : in dmem_in_array_type(G_NUM_SLAVES - 1 downto 0);
    clk_i : std_logic
    clk_i : std_logic
);
);
END core_address_decoder;
end core_address_decoder;
 
 
ARCHITECTURE arch OF core_address_decoder IS
architecture arch of core_address_decoder is
 
 
    -- Decodes the address based on the memory map. Returns "1" if 0 or 1 slave is attached.
    -- Decodes the address based on the memory map. Returns "1" if 0 or 1 slave is attached.
    FUNCTION decode(adr : std_logic_vector) RETURN std_logic_vector IS
    function decode(adr : std_logic_vector) return std_logic_vector is
        VARIABLE result : std_logic_vector(G_NUM_SLAVES - 1 DOWNTO 0);
        variable result : std_logic_vector(G_NUM_SLAVES - 1 downto 0);
    BEGIN
    begin
        result := (OTHERS => '1');
        if G_NUM_SLAVES > 1 and notx(adr) then
        IF G_NUM_SLAVES > 1 AND notx(adr) THEN
            for i in G_NUM_SLAVES - 1 downto 0 loop
            FOR i IN G_NUM_SLAVES - 1 DOWNTO 0 LOOP
                if (adr >= G_MEMORY_MAP(i) and adr < G_MEMORY_MAP(i+1)) then
                IF (adr >= G_MEMORY_MAP(i) AND adr < G_MEMORY_MAP(i+1)) THEN
 
                    result(i) := '1';
                    result(i) := '1';
                ELSE
                else
                    result(i) := '0';
                    result(i) := '0';
                END IF;
                end if;
            END LOOP;
            end loop;
        END IF;
        else
        RETURN result;
            result := (others => '1');
    END FUNCTION;
        end if;
 
        return result;
    FUNCTION demux(dmem_i : dmem_in_array_type; ce, r_ce : std_logic_vector) RETURN dmem_in_type IS
    end function;
        VARIABLE dmem : dmem_in_type;
 
    BEGIN
    function demux(dmem_i : dmem_in_array_type; ce, r_ce : std_logic_vector) return dmem_in_type is
 
        variable dmem : dmem_in_type;
 
    begin
        dmem := dmem_i(0);
        dmem := dmem_i(0);
        IF notx(ce) THEN
        if notx(ce) then
            FOR i IN G_NUM_SLAVES - 1 DOWNTO 0 LOOP
            for i in G_NUM_SLAVES - 1 downto 0 loop
                IF ce(i) = '1' THEN
                if ce(i) = '1' then
                    dmem.ena_i := dmem_i(i).ena_i;
                    dmem.ena_i := dmem_i(i).ena_i;
                END IF;
                end if;
                IF r_ce(i) = '1' THEN
                if r_ce(i) = '1' then
                    dmem.dat_i := dmem_i(i).dat_i;
                    dmem.dat_i := dmem_i(i).dat_i;
                END IF;
                end if;
            END LOOP;
            end loop;
        END IF;
        end if;
        RETURN dmem;
        return dmem;
    END FUNCTION;
    end function;
 
 
    SIGNAL r_ce, ce : std_logic_vector(G_NUM_SLAVES - 1 DOWNTO 0) := (OTHERS => '1');
    signal r_ce, ce : std_logic_vector(G_NUM_SLAVES - 1 downto 0) := (others => '1');
 
 
BEGIN
begin
 
 
    ce <= decode(m_dmem_o.adr_o);
    ce <= decode(m_dmem_o.adr_o);
    m_dmem_i <= demux(s_dmem_i, ce, r_ce);
    m_dmem_i <= demux(s_dmem_i, ce, r_ce);
 
 
    CON: FOR i IN G_NUM_SLAVES-1 DOWNTO 0 GENERATE
    CON: for i in G_NUM_SLAVES-1 downto 0 generate
    BEGIN
    begin
        s_dmem_o(i).dat_o <= m_dmem_o.dat_o;
        s_dmem_o(i).dat_o <= m_dmem_o.dat_o;
        s_dmem_o(i).adr_o <= m_dmem_o.adr_o;
        s_dmem_o(i).adr_o <= m_dmem_o.adr_o;
        s_dmem_o(i).sel_o <= m_dmem_o.sel_o;
        s_dmem_o(i).sel_o <= m_dmem_o.sel_o;
        s_dmem_o(i).we_o  <= m_dmem_o.we_o AND ce(i);
        s_dmem_o(i).we_o  <= m_dmem_o.we_o and ce(i);
        s_dmem_o(i).ena_o <= m_dmem_o.ena_o AND ce(i);
        s_dmem_o(i).ena_o <= m_dmem_o.ena_o and ce(i);
    END GENERATE;
    end generate;
 
 
    PROCESS(clk_i)
    process(clk_i)
    BEGIN
    begin
        IF rising_edge(clk_i) THEN
        if rising_edge(clk_i) then
            r_ce <= ce;
            r_ce <= ce;
        END IF;
        end if;
    END PROCESS;
    end process;
END arch;
end arch;
 
 
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