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-- Description : Top level module of the MB-Lite microprocessor with connected
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-- Description : Top level module of the MB-Lite microprocessor with connected
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-- wishbone data bus
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-- wishbone data bus
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--
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--
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----------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------
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LIBRARY ieee;
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library ieee;
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USE ieee.std_logic_1164.ALL;
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use ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.ALL;
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use ieee.std_logic_unsigned.all;
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LIBRARY mblite;
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library mblite;
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USE mblite.config_Pkg.ALL;
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use mblite.config_Pkg.all;
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USE mblite.core_Pkg.ALL;
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use mblite.core_Pkg.all;
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USE mblite.std_Pkg.ALL;
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use mblite.std_Pkg.all;
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ENTITY core_wb IS GENERIC
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entity core_wb is generic
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(
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(
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G_INTERRUPT : boolean := CFG_INTERRUPT;
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G_INTERRUPT : boolean := CFG_INTERRUPT;
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G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
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G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
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G_USE_BARREL : boolean := CFG_USE_BARREL;
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G_USE_BARREL : boolean := CFG_USE_BARREL;
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G_DEBUG : boolean := CFG_DEBUG
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G_DEBUG : boolean := CFG_DEBUG
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);
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);
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PORT
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port
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(
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(
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imem_o : OUT imem_out_type;
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imem_o : out imem_out_type;
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wb_o : OUT wb_mst_out_type;
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wb_o : out wb_mst_out_type;
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imem_i : IN imem_in_type;
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imem_i : in imem_in_type;
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wb_i : IN wb_mst_in_type
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wb_i : in wb_mst_in_type
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);
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);
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END core_wb;
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end core_wb;
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ARCHITECTURE arch OF core_wb IS
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architecture arch of core_wb is
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SIGNAL dmem_i : dmem_in_type;
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signal dmem_i : dmem_in_type;
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SIGNAL dmem_o : dmem_out_type;
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signal dmem_o : dmem_out_type;
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BEGIN
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begin
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wb_adapter0 : core_wb_adapter PORT MAP
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wb_adapter0 : core_wb_adapter port map
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(
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(
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dmem_i => dmem_i,
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dmem_i => dmem_i,
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wb_o => wb_o,
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wb_o => wb_o,
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dmem_o => dmem_o,
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dmem_o => dmem_o,
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wb_i => wb_i
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wb_i => wb_i
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);
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);
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core0 : core GENERIC MAP
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core0 : core generic map
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(
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(
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G_INTERRUPT => G_INTERRUPT,
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G_INTERRUPT => G_INTERRUPT,
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G_USE_HW_MUL => G_USE_HW_MUL,
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G_USE_HW_MUL => G_USE_HW_MUL,
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G_USE_BARREL => G_USE_BARREL,
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G_USE_BARREL => G_USE_BARREL,
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G_DEBUG => G_DEBUG
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G_DEBUG => G_DEBUG
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)
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)
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PORT MAP
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port map
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(
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(
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imem_o => imem_o,
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imem_o => imem_o,
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dmem_o => dmem_o,
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dmem_o => dmem_o,
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imem_i => imem_i,
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imem_i => imem_i,
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dmem_i => dmem_i,
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dmem_i => dmem_i,
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int_i => wb_i.int_i,
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int_i => wb_i.int_i,
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rst_i => wb_i.rst_i,
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rst_i => wb_i.rst_i,
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clk_i => wb_i.clk_i
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clk_i => wb_i.clk_i
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);
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);
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END arch;
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end arch;
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No newline at end of file
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