OpenCores
URL https://opencores.org/ocsvn/mblite/mblite/trunk

Subversion Repositories mblite

[/] [mblite/] [trunk/] [hw/] [std/] [std_Pkg.vhd] - Diff between revs 2 and 6

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 2 Rev 6
Line 26... Line 26...
        WIDTH : positive;
        WIDTH : positive;
        SIZE  : positive
        SIZE  : positive
    );
    );
    PORT
    PORT
    (
    (
        dat_o : OUT std_ulogic_vector(WIDTH - 1 DOWNTO 0);
        dat_o : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
        dat_i : IN std_ulogic_vector(WIDTH - 1 DOWNTO 0);
        dat_i : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
        adr_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
        adr_i : IN std_logic_vector(SIZE - 1 DOWNTO 0);
        wre_i : IN std_ulogic;
        wre_i : IN std_logic;
        ena_i : IN std_ulogic;
        ena_i : IN std_logic;
        clk_i : IN std_ulogic
        clk_i : IN std_logic
    );
    );
    END COMPONENT;
    END COMPONENT;
 
 
    COMPONENT sram_4en GENERIC
    COMPONENT sram_4en GENERIC
    (
    (
        WIDTH : positive;
        WIDTH : positive;
        SIZE  : positive
        SIZE  : positive
    );
    );
    PORT
    PORT
    (
    (
        dat_o : OUT std_ulogic_vector(WIDTH - 1 DOWNTO 0);
        dat_o : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
        dat_i : IN std_ulogic_vector(WIDTH - 1 DOWNTO 0);
        dat_i : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
        adr_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
        adr_i : IN std_logic_vector(SIZE - 1 DOWNTO 0);
        wre_i : IN std_ulogic_vector(3 DOWNTO 0);
        wre_i : IN std_logic_vector(3 DOWNTO 0);
        ena_i : IN std_ulogic;
        ena_i : IN std_logic;
        clk_i : IN std_ulogic
        clk_i : IN std_logic
    );
    );
    END COMPONENT;
    END COMPONENT;
 
 
    COMPONENT dsram GENERIC
    COMPONENT dsram GENERIC
    (
    (
        WIDTH : positive;
        WIDTH : positive;
        SIZE  : positive
        SIZE  : positive
    );
    );
    PORT
    PORT
    (
    (
        dat_o   : OUT std_ulogic_vector(WIDTH - 1 DOWNTO 0);
        dat_o   : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
        adr_i   : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
        adr_i   : IN std_logic_vector(SIZE - 1 DOWNTO 0);
        ena_i   : IN std_ulogic;
        ena_i   : IN std_logic;
        dat_w_i : IN std_ulogic_vector(WIDTH - 1 DOWNTO 0);
        dat_w_i : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
        adr_w_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
        adr_w_i : IN std_logic_vector(SIZE - 1 DOWNTO 0);
        wre_i   : IN std_ulogic;
        wre_i   : IN std_logic;
        clk_i   : IN std_ulogic
        clk_i   : IN std_logic
    );
    );
    END COMPONENT;
    END COMPONENT;
 
 
----------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------
-- FUNCTIONS IN STD_PKG
-- FUNCTIONS IN STD_PKG
----------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------
 
 
    FUNCTION v_or(d : std_ulogic_vector) RETURN std_ulogic;
    FUNCTION v_or(d : std_logic_vector) RETURN std_logic;
    FUNCTION is_zero(d : std_ulogic_vector) RETURN std_ulogic;
    FUNCTION is_zero(d : std_logic_vector) RETURN std_logic;
    FUNCTION is_not_zero(d : std_ulogic_vector) RETURN std_ulogic;
    FUNCTION is_not_zero(d : std_logic_vector) RETURN std_logic;
    FUNCTION my_conv_integer(a: std_ulogic_vector) RETURN integer;
    FUNCTION my_conv_integer(a: std_logic_vector) RETURN integer;
    FUNCTION notx(d : std_ulogic_vector) RETURN boolean;
    FUNCTION notx(d : std_logic_vector) RETURN boolean;
    FUNCTION compare(a, b : std_ulogic_vector) RETURN std_ulogic;
    FUNCTION compare(a, b : std_logic_vector) RETURN std_logic;
    FUNCTION multiply(a, b : std_ulogic_vector) RETURN std_ulogic_vector;
    FUNCTION multiply(a, b : std_logic_vector) RETURN std_logic_vector;
    FUNCTION sign_extend(value: std_ulogic_vector; fill: std_ulogic; size: positive) RETURN std_ulogic_vector;
    FUNCTION sign_extend(value: std_logic_vector; fill: std_logic; size: positive) RETURN std_logic_vector;
    FUNCTION add(a, b : std_ulogic_vector; ci: std_ulogic) RETURN std_ulogic_vector;
    FUNCTION add(a, b : std_logic_vector; ci: std_logic) RETURN std_logic_vector;
    FUNCTION increment(a : std_ulogic_vector) RETURN std_ulogic_vector;
    FUNCTION increment(a : std_logic_vector) RETURN std_logic_vector;
    FUNCTION shift(value : std_ulogic_vector(31 DOWNTO 0); shamt: std_ulogic_vector(4 DOWNTO 0); s: std_ulogic; t: std_ulogic) RETURN std_ulogic_vector;
    FUNCTION shift(value : std_logic_vector(31 DOWNTO 0); shamt: std_logic_vector(4 DOWNTO 0); s: std_logic; t: std_logic) RETURN std_logic_vector;
    FUNCTION shift_left(value : std_ulogic_vector(31 DOWNTO 0); shamt : std_ulogic_vector(4 DOWNTO 0)) RETURN std_ulogic_vector;
    FUNCTION shift_left(value : std_logic_vector(31 DOWNTO 0); shamt : std_logic_vector(4 DOWNTO 0)) RETURN std_logic_vector;
    FUNCTION shift_right(value : std_ulogic_vector(31 DOWNTO 0); shamt : std_ulogic_vector(4 DOWNTO 0); padding: std_ulogic) RETURN std_ulogic_vector;
    FUNCTION shift_right(value : std_logic_vector(31 DOWNTO 0); shamt : std_logic_vector(4 DOWNTO 0); padding: std_logic) RETURN std_logic_vector;
 
 
END std_Pkg;
END std_Pkg;
 
 
PACKAGE BODY std_Pkg IS
PACKAGE BODY std_Pkg IS
 
 
-- Unary OR reduction
-- Unary OR reduction
    FUNCTION v_or(d : std_ulogic_vector) RETURN std_ulogic IS
    FUNCTION v_or(d : std_logic_vector) RETURN std_logic IS
        VARIABLE z : std_ulogic;
        VARIABLE z : std_logic;
    BEGIN
    BEGIN
        z := '0';
        z := '0';
        IF notx (d) THEN
        IF notx (d) THEN
            FOR i IN d'range LOOP
            FOR i IN d'range LOOP
                z := z OR d(i);
                z := z OR d(i);
Line 104... Line 104...
        END IF;
        END IF;
        RETURN z;
        RETURN z;
    END;
    END;
 
 
-- Check for ones in the vector
-- Check for ones in the vector
    FUNCTION is_not_zero(d : std_ulogic_vector) RETURN std_ulogic IS
    FUNCTION is_not_zero(d : std_logic_vector) RETURN std_logic IS
        VARIABLE z : std_ulogic_vector(d'range);
        VARIABLE z : std_logic_vector(d'range);
    BEGIN
    BEGIN
        z := (OTHERS => '0');
        z := (OTHERS => '0');
        IF notx(d) THEN
        IF notx(d) THEN
 
 
            IF d = z THEN
            IF d = z THEN
Line 122... Line 122...
            RETURN '0';
            RETURN '0';
        END IF;
        END IF;
    END;
    END;
 
 
-- Check for ones in the vector
-- Check for ones in the vector
    FUNCTION is_zero(d : std_ulogic_vector) RETURN std_ulogic IS
    FUNCTION is_zero(d : std_logic_vector) RETURN std_logic IS
    BEGIN
    BEGIN
        RETURN NOT is_not_zero(d);
        RETURN NOT is_not_zero(d);
    END;
    END;
 
 
    -- rewrite conv_integer to avoid modelsim warnings
    -- rewrite conv_integer to avoid modelsim warnings
    FUNCTION my_conv_integer(a : std_ulogic_vector) RETURN integer IS
    FUNCTION my_conv_integer(a : std_logic_vector) RETURN integer IS
        VARIABLE res : integer RANGE 0 TO 2**a'length-1;
        VARIABLE res : integer RANGE 0 TO 2**a'length-1;
    BEGIN
    BEGIN
        res := 0;
        res := 0;
        IF (notx(a)) THEN
        IF (notx(a)) THEN
            res := to_integer(unsigned(a));
            res := to_integer(unsigned(a));
        END IF;
        END IF;
        RETURN res;
        RETURN res;
    END;
    END;
 
 
    FUNCTION compare(a, b : std_ulogic_vector) RETURN std_ulogic IS
    FUNCTION compare(a, b : std_logic_vector) RETURN std_logic IS
        VARIABLE z : std_ulogic;
        VARIABLE z : std_logic;
    BEGIN
    BEGIN
 
 
        IF notx(a & b) AND a = b THEN
        IF notx(a & b) AND a = b THEN
            RETURN '1';
            RETURN '1';
        ELSE
        ELSE
Line 151... Line 151...
        END IF;
        END IF;
 
 
    END;
    END;
 
 
-- Unary NOT X test
-- Unary NOT X test
    FUNCTION notx(d : std_ulogic_vector) RETURN boolean IS
    FUNCTION notx(d : std_logic_vector) RETURN boolean IS
        VARIABLE res : boolean;
        VARIABLE res : boolean;
    BEGIN
    BEGIN
        res := true;
        res := true;
-- pragma translate_off
-- pragma translate_off
        res := NOT is_x(d);
        res := NOT is_x(d);
Line 180... Line 180...
-- --         else
-- --         else
-- --              (rD) ← (rA)
-- --              (rD) ← (rA)
-- --      else
-- --      else
-- --         (rD) ← (rA) >> (rB)[27:31]
-- --         (rD) ← (rA) >> (rB)[27:31]
 
 
    FUNCTION shift(value: std_ulogic_vector(31 DOWNTO 0); shamt: std_ulogic_vector(4 DOWNTO 0); s: std_ulogic; t: std_ulogic) RETURN std_ulogic_vector IS
    FUNCTION shift(value: std_logic_vector(31 DOWNTO 0); shamt: std_logic_vector(4 DOWNTO 0); s: std_logic; t: std_logic) RETURN std_logic_vector IS
    BEGIN
    BEGIN
        IF s = '1' THEN
        IF s = '1' THEN
            -- left arithmetic or logical shift
            -- left arithmetic or logical shift
            RETURN shift_left(value, shamt);
            RETURN shift_left(value, shamt);
        ELSE
        ELSE
Line 196... Line 196...
                RETURN shift_right(value, shamt, '0');
                RETURN shift_right(value, shamt, '0');
            END IF;
            END IF;
        END IF;
        END IF;
    END;
    END;
 
 
    FUNCTION shift_left(value: std_ulogic_vector(31 DOWNTO 0); shamt: std_ulogic_vector(4 DOWNTO 0)) RETURN std_ulogic_vector IS
    FUNCTION shift_left(value: std_logic_vector(31 DOWNTO 0); shamt: std_logic_vector(4 DOWNTO 0)) RETURN std_logic_vector IS
        VARIABLE result: std_ulogic_vector(31 DOWNTO 0);
        VARIABLE result: std_logic_vector(31 DOWNTO 0);
        VARIABLE paddings: std_ulogic_vector(15 DOWNTO 0);
        VARIABLE paddings: std_logic_vector(15 DOWNTO 0);
    BEGIN
    BEGIN
 
 
        paddings := (OTHERS => '0');
        paddings := (OTHERS => '0');
        result := value;
        result := value;
        IF (shamt(4) = '1') THEN result := result(15 DOWNTO 0) & paddings(15 DOWNTO 0); END IF;
        IF (shamt(4) = '1') THEN result := result(15 DOWNTO 0) & paddings(15 DOWNTO 0); END IF;
Line 212... Line 212...
        IF (shamt(0) = '1') THEN result := result(30 DOWNTO 0) & paddings( 0 );         END IF;
        IF (shamt(0) = '1') THEN result := result(30 DOWNTO 0) & paddings( 0 );         END IF;
        RETURN result;
        RETURN result;
 
 
    END;
    END;
 
 
    FUNCTION shift_right(value: std_ulogic_vector(31 DOWNTO 0); shamt: std_ulogic_vector(4 DOWNTO 0); padding: std_ulogic) RETURN std_ulogic_vector IS
    FUNCTION shift_right(value: std_logic_vector(31 DOWNTO 0); shamt: std_logic_vector(4 DOWNTO 0); padding: std_logic) RETURN std_logic_vector IS
        VARIABLE result: std_ulogic_vector(31 DOWNTO 0);
        VARIABLE result: std_logic_vector(31 DOWNTO 0);
        VARIABLE paddings: std_ulogic_vector(15 DOWNTO 0);
        VARIABLE paddings: std_logic_vector(15 DOWNTO 0);
    BEGIN
    BEGIN
 
 
        paddings := (OTHERS => padding);
        paddings := (OTHERS => padding);
        result := value;
        result := value;
        IF (shamt(4) = '1') THEN result := paddings(15 DOWNTO 0) & result(31 DOWNTO 16); END IF;
        IF (shamt(4) = '1') THEN result := paddings(15 DOWNTO 0) & result(31 DOWNTO 16); END IF;
Line 228... Line 228...
        IF (shamt(0) = '1') THEN result := paddings( 0 )         & result(31 DOWNTO  1); END IF;
        IF (shamt(0) = '1') THEN result := paddings( 0 )         & result(31 DOWNTO  1); END IF;
        RETURN result;
        RETURN result;
 
 
    END;
    END;
 
 
    FUNCTION multiply(a, b: std_ulogic_vector) RETURN std_ulogic_vector IS
    FUNCTION multiply(a, b: std_logic_vector) RETURN std_logic_vector IS
        VARIABLE x: std_ulogic_vector (a'length + b'length - 1 DOWNTO 0);
        VARIABLE x: std_logic_vector (a'length + b'length - 1 DOWNTO 0);
    BEGIN
    BEGIN
        x := std_ulogic_vector(signed(a) * signed(b));
        x := std_logic_vector(signed(a) * signed(b));
        RETURN x(31 DOWNTO 0);
        RETURN x(31 DOWNTO 0);
    END;
    END;
 
 
    FUNCTION sign_extend(value: std_ulogic_vector; fill: std_ulogic; size: positive) RETURN std_ulogic_vector IS
    FUNCTION sign_extend(value: std_logic_vector; fill: std_logic; size: positive) RETURN std_logic_vector IS
        VARIABLE a: std_ulogic_vector (size - 1 DOWNTO 0);
        VARIABLE a: std_logic_vector (size - 1 DOWNTO 0);
    BEGIN
    BEGIN
        a(size - 1 DOWNTO value'length) := (OTHERS => fill);
        a(size - 1 DOWNTO value'length) := (OTHERS => fill);
        a(value'length - 1 DOWNTO 0) := value;
        a(value'length - 1 DOWNTO 0) := value;
        return a;
        return a;
    END;
    END;
 
 
    FUNCTION add(a, b : std_ulogic_vector; ci: std_ulogic) RETURN std_ulogic_vector IS
    FUNCTION add(a, b : std_logic_vector; ci: std_logic) RETURN std_logic_vector IS
        VARIABLE x : std_ulogic_vector(a'length + 1 DOWNTO 0);
        VARIABLE x : std_logic_vector(a'length + 1 DOWNTO 0);
    BEGIN
    BEGIN
        x := (OTHERS => '0');
        x := (OTHERS => '0');
        IF notx (a & b & ci) THEN
        IF notx (a & b & ci) THEN
            x := std_ulogic_vector(signed('0' & a & '1') + signed('0' & b & ci));
            x := std_logic_vector(signed('0' & a & '1') + signed('0' & b & ci));
        END IF;
        END IF;
        RETURN x(a'length + 1 DOWNTO 1);
        RETURN x(a'length + 1 DOWNTO 1);
    END;
    END;
 
 
    FUNCTION increment(a : std_ulogic_vector) RETURN std_ulogic_vector IS
    FUNCTION increment(a : std_logic_vector) RETURN std_logic_vector IS
        VARIABLE x : std_ulogic_vector(a'length-1 DOWNTO 0);
        VARIABLE x : std_logic_vector(a'length-1 DOWNTO 0);
    BEGIN
    BEGIN
        x := (OTHERS => '0');
        x := (OTHERS => '0');
        IF notx (a) THEN
        IF notx (a) THEN
            x := std_ulogic_vector(signed(a) + 1);
            x := std_logic_vector(signed(a) + 1);
        END IF;
        END IF;
        RETURN x;
        RETURN x;
    END;
    END;
 
 
END std_Pkg;
END std_Pkg;
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.