OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [rc-1.0/] [backend/] [altera_3c25_board/] [orp.ld] - Diff between revs 93 and 109

Go to most recent revision | Only display areas with differences | Details | Blame | View Log

Rev 93 Rev 109
MEMORY
MEMORY
        {
        {
        reset   : ORIGIN = 0x00000000, LENGTH = 0x00000200
        reset   : ORIGIN = 0x00000000, LENGTH = 0x00000200
        vectors : ORIGIN = 0x00000200, LENGTH = 0x00001000
        vectors : ORIGIN = 0x00000200, LENGTH = 0x00001000
    ram     : ORIGIN = 0x00001200, LENGTH = 0x0001EE00  /*0x20000 total*/
    ram     : ORIGIN = 0x00001200, LENGTH = 0x0001EE00  /*0x20000 total*/
        }
        }
SECTIONS
SECTIONS
{
{
        .reset :
        .reset :
        {
        {
        *(.reset)
        *(.reset)
        } > reset
        } > reset
        .vectors :
        .vectors :
        {
        {
        _vec_start = .;
        _vec_start = .;
        *(.vectors)
        *(.vectors)
        _vec_end = .;
        _vec_end = .;
        } > vectors
        } > vectors
        .text :
        .text :
        {
        {
        *(.text)
        *(.text)
        } > ram
        } > ram
      .rodata :
      .rodata :
        {
        {
        *(.rodata)
        *(.rodata)
        *(.rodata.*)
        *(.rodata.*)
        } > ram
        } > ram
     .icm :
     .icm :
        {
        {
        _icm_start = .;
        _icm_start = .;
        *(.icm)
        *(.icm)
        _icm_end = .;
        _icm_end = .;
        } > ram
        } > ram
     .data :
     .data :
        {
        {
        _dst_beg = .;
        _dst_beg = .;
        *(.data)
        *(.data)
        _dst_end = .;
        _dst_end = .;
        } > ram
        } > ram
      .bss :
      .bss :
        {
        {
        *(.bss)
        *(.bss)
        } > ram
        } > ram
      .stack (NOLOAD) :
      .stack (NOLOAD) :
        {
        {
        *(.stack)
        *(.stack)
        _src_addr = .;
        _src_addr = .;
        } > ram
        } > ram
}
}
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2023 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.