OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [rc-1.0/] [backend/] [spartan3e_starter_kit/] [or1200_defines.v] - Diff between revs 113 and 117

Show entire file | Details | Blame | View Log

Rev 113 Rev 117
Line 579... Line 579...
//
//
// Memory macro w/ two ports (see or1200_tpram_32x32.v)
// Memory macro w/ two ports (see or1200_tpram_32x32.v)
//`define OR1200_RFRAM_TWOPORT
//`define OR1200_RFRAM_TWOPORT
//
//
// Memory macro dual port (see or1200_dpram_32x32.v)
// Memory macro dual port (see or1200_dpram_32x32.v)
//`define OR1200_RFRAM_DUALPORT
`define OR1200_RFRAM_DUALPORT
//
//
// Generic (flip-flop based) register file (see or1200_rfram_generic.v)
// Generic (flip-flop based) register file (see or1200_rfram_generic.v)
`define OR1200_RFRAM_GENERIC
//`define OR1200_RFRAM_GENERIC
 
 
//
//
// Type of mem2reg aligner to implement.
// Type of mem2reg aligner to implement.
//
//
// Once OR1200_IMPL_MEM2REG2 yielded faster
// Once OR1200_IMPL_MEM2REG2 yielded faster

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.