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//
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//
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// Define FPGA manufacturer
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// Define FPGA manufacturer
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//
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//
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//`define GENERIC_FPGA
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//`define GENERIC_FPGA
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//`define ALTERA_FPGA
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`define ALTERA_FPGA
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`define XILINX_FPGA
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//`define XILINX_FPGA
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//
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//
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// Define FPGA Model (comment all out for ALTERA)
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// Define FPGA Model (comment all out for ALTERA)
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//
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//
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//`define SPARTAN2
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//`define SPARTAN2
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//`define SPARTAN3
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//`define SPARTAN3
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//`define SPARTAN3E
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//`define SPARTAN3E
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`define SPARTAN3A
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//`define SPARTAN3A
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//`define VIRTEX
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//`define VIRTEX
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//`define VIRTEX2
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//`define VIRTEX2
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//`define VIRTEX4
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//`define VIRTEX4
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//`define VIRTEX5
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//`define VIRTEX5
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//
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// Define Altera FPGA Family (comment all out for XILINX)
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//`define ARRIA_GX
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//`define ARRIA_II_GX
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//`define CYCLONE_I
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//`define CYCLONE_II
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`define CYCLONE_III
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//`define CYCLONE_III_LS
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//`define CYCLONE_IV_E
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//`define CYCLONE_IV_GS
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//`define MAX_II
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//`define MAX_V
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//`define MAX3000A
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//`define MAX7000AE
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//`define MAX7000B
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//`define MAX7000S
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//`define STRATIX
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//`define STRATIX_II
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//`define STRATIX_II_GX
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//`define STRATIX_III
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//
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//
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// Memory
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// Memory
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//
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//
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`define MEMORY_ADR_WIDTH 13 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, memory is composed by blocks of address width 11
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`define MEMORY_ADR_WIDTH 13 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, memory is composed by blocks of address width 11
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// Clock Division selection
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// Clock Division selection
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//
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//
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//`define NO_CLOCK_DIVISION
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//`define NO_CLOCK_DIVISION
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//`define GENERIC_CLOCK_DIVISION
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//`define GENERIC_CLOCK_DIVISION
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`define FPGA_CLOCK_DIVISION // Altera ALTPLL is yet implemented in Verilog and will be used with this option
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`define FPGA_CLOCK_DIVISION // Altera ALTPLL is yet implemented in Verilog and will be used with this option
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// Note that only CYCLONE_III family has been tested.
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//
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//
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// Define division
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// Define division
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//
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//
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`define CLOCK_DIVISOR 4 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded down to an even value
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`define CLOCK_DIVISOR 1 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded down to an even value
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//in FPGA case, check minsoc_clock_manager for allowed divisors
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//in FPGA case, check minsoc_clock_manager for allowed divisors
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//DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION INSTEAD
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//DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION INSTEAD
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//
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//
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// Define multiply
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//
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`define CLOCK_MULTIPLIER 2 // In case of FPGA_CLOCK_DIVISION for Altera FPGAs, ALTPLL Megafunction will be used
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// and this will need a clock multiply factor.
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//
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// Reset polarity
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// Reset polarity
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//
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//
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//`define NEGATIVE_RESET //rstn
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`define NEGATIVE_RESET //rstn
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`define POSITIVE_RESET //rst
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//`define POSITIVE_RESET //rst
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//
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//
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// Start-up circuit (only necessary later to load firmware automatically from SPI memory)
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// Start-up circuit (only necessary later to load firmware automatically from SPI memory)
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//
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//
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//`define START_UP
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//`define START_UP
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