URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 56 |
Rev 57 |
| Line 1... |
Line 1... |
//
|
//
|
// Define FPGA manufacturer
|
// Define FPGA manufacturer
|
//
|
//
|
//`define GENERIC_FPGA
|
//`define GENERIC_FPGA
|
`define ALTERA_FPGA
|
//`define ALTERA_FPGA
|
//`define XILINX_FPGA
|
`define XILINX_FPGA
|
|
|
//
|
//
|
// Define FPGA Model (comment all out for ALTERA)
|
// Define Xilinx FPGA family
|
//
|
//
|
|
`ifdef XILINX_FPGA
|
//`define SPARTAN2
|
//`define SPARTAN2
|
//`define SPARTAN3
|
//`define SPARTAN3
|
//`define SPARTAN3E
|
//`define SPARTAN3E
|
//`define SPARTAN3A
|
`define SPARTAN3A
|
//`define VIRTEX
|
//`define VIRTEX
|
//`define VIRTEX2
|
//`define VIRTEX2
|
//`define VIRTEX4
|
//`define VIRTEX4
|
//`define VIRTEX5
|
//`define VIRTEX5
|
|
|
//
|
//
|
// Define Altera FPGA Family (comment all out for XILINX)
|
// Define Altera FPGA family
|
|
//
|
|
`elsif ALTERA_FPGA
|
//`define ARRIA_GX
|
//`define ARRIA_GX
|
//`define ARRIA_II_GX
|
//`define ARRIA_II_GX
|
//`define CYCLONE_I
|
//`define CYCLONE_I
|
//`define CYCLONE_II
|
//`define CYCLONE_II
|
`define CYCLONE_III
|
`define CYCLONE_III
|
| Line 35... |
Line 38... |
//`define MAX7000S
|
//`define MAX7000S
|
//`define STRATIX
|
//`define STRATIX
|
//`define STRATIX_II
|
//`define STRATIX_II
|
//`define STRATIX_II_GX
|
//`define STRATIX_II_GX
|
//`define STRATIX_III
|
//`define STRATIX_III
|
|
`endif
|
|
|
//
|
//
|
// Memory
|
// Memory
|
//
|
//
|
`define MEMORY_ADR_WIDTH 13 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, memory is composed by blocks of address width 11
|
`define MEMORY_ADR_WIDTH 13 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, memory is composed by blocks of address width 11
|
| Line 63... |
Line 67... |
//
|
//
|
// Clock Division selection
|
// Clock Division selection
|
//
|
//
|
//`define NO_CLOCK_DIVISION
|
//`define NO_CLOCK_DIVISION
|
//`define GENERIC_CLOCK_DIVISION
|
//`define GENERIC_CLOCK_DIVISION
|
`define FPGA_CLOCK_DIVISION // Altera ALTPLL is yet implemented in Verilog and will be used with this option
|
`define FPGA_CLOCK_DIVISION // For Altera ALTPLL, only CYCLONE_III family has been tested.
|
// Note that only CYCLONE_III family has been tested.
|
|
|
|
//
|
//
|
// Define division
|
// Define division
|
//
|
//
|
`define CLOCK_DIVISOR 1 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded down to an even value
|
`define CLOCK_DIVISOR 5 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded down to an even value
|
//in FPGA case, check minsoc_clock_manager for allowed divisors
|
//in FPGA case, check minsoc_clock_manager for allowed divisors
|
//DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION INSTEAD
|
//DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION INSTEAD
|
|
|
//
|
//
|
// Reset polarity
|
// Reset polarity
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.