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//
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//
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// Define FPGA manufacturer
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// Define FPGA manufacturer
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//
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//
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//`define GENERIC_FPGA
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`define GENERIC_FPGA
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//`define ALTERA_FPGA
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//`define ALTERA_FPGA
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`define XILINX_FPGA
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//`define XILINX_FPGA
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//
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//
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// Define Xilinx FPGA family
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// Define Xilinx FPGA family
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//
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//
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`ifdef XILINX_FPGA
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`ifdef XILINX_FPGA
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`endif
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`endif
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//
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//
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// Memory
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// Memory
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//
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//
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`define MEMORY_ADR_WIDTH 13 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, memory is composed by blocks of address width 11
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`define MEMORY_ADR_WIDTH 13 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12,
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//Address width of memory -> select memory depth, 2 powers MEMORY_ADR_WIDTH defines the memory depth
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//memory is composed by blocks of address width 11
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//the memory data width is 32 bit, memory amount in Bytes = 4*memory depth
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//Address width of memory -> select memory depth,
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//2 powers MEMORY_ADR_WIDTH defines the memory depth
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//the memory data width is 32 bit,
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//memory amount in Bytes = 4*memory depth
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//
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//
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// Memory type (uncomment something if ASIC or generic memory)
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// Memory type (uncomment something if ASIC or generic memory)
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//
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//
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//`define GENERIC_MEMORY
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//`define GENERIC_MEMORY
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`define FPGA_CLOCK_DIVISION // For Altera ALTPLL, only CYCLONE_III family has been tested.
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`define FPGA_CLOCK_DIVISION // For Altera ALTPLL, only CYCLONE_III family has been tested.
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//
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//
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// Define division
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// Define division
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//
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//
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`define CLOCK_DIVISOR 5 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded down to an even value
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`define CLOCK_DIVISOR 5 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded
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//in FPGA case, check minsoc_clock_manager for allowed divisors
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//down to an even value in FPGA case, check minsoc_clock_manager
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//DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION INSTEAD
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//for allowed divisors.
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//DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION
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//INSTEAD.
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//
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//
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// Reset polarity
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// Reset polarity
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//
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//
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//`define NEGATIVE_RESET //rstn
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`define NEGATIVE_RESET //rstn
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`define POSITIVE_RESET //rst
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//`define POSITIVE_RESET //rst
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//
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//
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// Start-up circuit (only necessary later to load firmware automatically from SPI memory)
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// Start-up circuit (only necessary later to load firmware automatically from SPI memory)
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//
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//
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//`define START_UP
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//`define START_UP
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//
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//
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// Connected modules
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// Connected modules
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//
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//
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`define UART
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`define UART
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//`define ETHERNET
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`define ETHERNET
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//
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//
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// Ethernet reset
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// Ethernet reset
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//
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//
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//`define ETH_RESET 1'b0
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`define ETH_RESET 1'b0
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`define ETH_RESET 1'b1
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//`define ETH_RESET 1'b1
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//
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//
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// Interrupts
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// Interrupts
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//
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//
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`define APP_INT_RES1 1:0
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`define APP_INT_RES1 1:0
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