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//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
////  OR1K test app definitions                                   ////
 
////                                                              ////
 
////  This file is part of the OR1K test application              ////
 
////  http://www.opencores.org/cores/or1k/xess/                   ////
 
////                                                              ////
 
////  Description                                                 ////
 
////  DEfine target technology etc. Right now FIFOs are available ////
 
////  only for Xilinx Virtex FPGAs. (TARGET_VIRTEX)               ////
 
////                                                              ////
 
////  To Do:                                                      ////
 
////   - nothing really                                           ////
 
////                                                              ////
 
////  Author(s):                                                  ////
 
////      - Damjan Lampret, damjan.lampret@opencores.org          ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
//// Copyright (C) 2001 Authors                                   ////
 
////                                                              ////
 
//// This source file may be used and distributed without         ////
 
//// restriction provided that this copyright statement is not    ////
 
//// removed from the file and that any derivative work contains  ////
 
//// the original copyright notice and the associated disclaimer. ////
 
////                                                              ////
 
//// This source file is free software; you can redistribute it   ////
 
//// and/or modify it under the terms of the GNU Lesser General   ////
 
//// Public License as published by the Free Software Foundation; ////
 
//// either version 2.1 of the License, or (at your option) any   ////
 
//// later version.                                               ////
 
////                                                              ////
 
//// This source is distributed in the hope that it will be       ////
 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
 
//// details.                                                     ////
 
////                                                              ////
 
//// You should have received a copy of the GNU Lesser General    ////
 
//// Public License along with this source; if not, download it   ////
 
//// from http://www.opencores.org/lgpl.shtml                     ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
//
 
// CVS Revision History
 
//
 
// $Log: xsv_fpga_defines.v,v $
 
// Revision 1.4  2004/04/05 08:44:35  lampret
 
// Merged branch_qmem into main tree.
 
//
 
// Revision 1.2  2002/03/29 20:58:51  lampret
 
// Changed hardcoded address for fake MC to use a define.
 
//
 
// Revision 1.1.1.1  2002/03/21 16:55:44  lampret
 
// First import of the "new" XESS XSV environment.
 
//
 
//
 
//
 
 
 
 
 
//
//
// Define FPGA manufacturer
// Define FPGA manufacturer
//
//
//`define GENERIC_FPGA
//`define GENERIC_FPGA
//`define ALTERA_FPGA
//`define ALTERA_FPGA
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`define MEMORY_ADR_WIDTH   13   //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, memory is composed by blocks of address width 11
`define MEMORY_ADR_WIDTH   13   //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, memory is composed by blocks of address width 11
                                                                //Address width of memory -> select memory depth, 2 powers MEMORY_ADR_WIDTH defines the memory depth 
                                                                //Address width of memory -> select memory depth, 2 powers MEMORY_ADR_WIDTH defines the memory depth 
                                                                //the memory data width is 32 bit, memory amount in Bytes = 4*memory depth
                                                                //the memory data width is 32 bit, memory amount in Bytes = 4*memory depth
 
 
//
//
// Memory type  (uncomment something if ASIC or if you want generic memory)
// Memory type  (uncomment something if ASIC or generic memory)
//
//
//`define GENERIC_MEMORY
//`define GENERIC_MEMORY
//`define AVANT_ATP
//`define AVANT_ATP
//`define VIRAGE_SSP
//`define VIRAGE_SSP
//`define VIRTUALSILICON_SSP
//`define VIRTUALSILICON_SSP
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`define CLOCK_DIVISOR 5         //in case of GENERIC_CLOCK_DIVISION the real value will be rounded down to an even value
`define CLOCK_DIVISOR 5         //in case of GENERIC_CLOCK_DIVISION the real value will be rounded down to an even value
                                                        //in FPGA case, check minsoc_clock_manager for allowed divisors
                                                        //in FPGA case, check minsoc_clock_manager for allowed divisors
                                                        //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION INSTEAD
                                                        //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION INSTEAD
 
 
//
//
 
// Reset polarity
 
//
 
//`define NEGATIVE_RESET;      //rstn
 
`define POSITIVE_RESET;      //rst
 
 
 
//
// Start-up circuit (only necessary later to load firmware automatically from SPI memory)
// Start-up circuit (only necessary later to load firmware automatically from SPI memory)
//
//
//`define START_UP
//`define START_UP
 
 
//
//

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