URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Show entire file |
Details |
Blame |
View Log
| Rev 146 |
Rev 147 |
| Line 4... |
Line 4... |
`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down)
|
`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down)
|
//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
|
//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
|
|
|
`define FREQ_NUM_FOR_NS 100000000
|
`define FREQ_NUM_FOR_NS 100000000
|
|
|
`define FREQ 25000000
|
`define FREQ 10000000
|
`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ)
|
`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ)
|
|
|
`define ETH_PHY_FREQ 25000000
|
`define ETH_PHY_FREQ 25000000
|
`define ETH_PHY_PERIOD (`FREQ_NUM_FOR_NS/`ETH_PHY_FREQ) //40ns
|
`define ETH_PHY_PERIOD (`FREQ_NUM_FOR_NS/`ETH_PHY_FREQ) //40ns
|
|
|
`define UART_BAUDRATE 115200
|
`define UART_BAUDRATE 9600
|
|
|
`define VPI_DEBUG
|
`define VPI_DEBUG
|
|
|
//`define VCD_OUTPUT
|
//`define WAVEFORM_OUTPUT
|
|
|
//`define START_UP //pass firmware over spi to or1k_startup
|
//`define START_UP //pass firmware over spi to or1k_startup
|
|
|
`define INITIALIZE_MEMORY_MODEL //instantaneously initialize memory model with firmware
|
`define INITIALIZE_MEMORY_MODEL //instantaneously initialize memory model with firmware
|
//only use with the memory model.
|
//only use with the memory model.
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.