OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [rc-1.0/] [rtl/] [verilog/] [altera_pll.v] - Diff between revs 52 and 56

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 52 Rev 56
Line 24... Line 24...
        inclk0,
        inclk0,
        c0);
        c0);
 
 
        parameter FREQ_MULT = 1;
        parameter FREQ_MULT = 1;
        parameter FREQ_DIV = 1;
        parameter FREQ_DIV = 1;
 
        parameter FAMILY = "Cyclone III";
 
 
        input     inclk0;
        input     inclk0;
        output    c0;
        output    c0;
 
 
        wire [4:0] sub_wire0;
        wire [4:0] sub_wire0;
Line 81... Line 82...
                altpll_component.clk0_duty_cycle = 50,
                altpll_component.clk0_duty_cycle = 50,
                altpll_component.clk0_multiply_by = FREQ_MULT,
                altpll_component.clk0_multiply_by = FREQ_MULT,
                altpll_component.clk0_phase_shift = "0",
                altpll_component.clk0_phase_shift = "0",
                altpll_component.compensate_clock = "CLK0",
                altpll_component.compensate_clock = "CLK0",
                altpll_component.inclk0_input_frequency = 20000,
                altpll_component.inclk0_input_frequency = 20000,
                altpll_component.intended_device_family = "Cyclone III",
                altpll_component.intended_device_family = FAMILY,
                altpll_component.lpm_hint = "CBX_MODULE_PREFIX=minsocPll",
                altpll_component.lpm_hint = "CBX_MODULE_PREFIX=minsocPll",
                altpll_component.lpm_type = "altpll",
                altpll_component.lpm_type = "altpll",
                altpll_component.operation_mode = "NORMAL",
                altpll_component.operation_mode = "NORMAL",
                altpll_component.pll_type = "AUTO",
                altpll_component.pll_type = "AUTO",
                altpll_component.port_activeclock = "PORT_UNUSED",
                altpll_component.port_activeclock = "PORT_UNUSED",
Line 128... Line 129...
                altpll_component.port_extclk0 = "PORT_UNUSED",
                altpll_component.port_extclk0 = "PORT_UNUSED",
                altpll_component.port_extclk1 = "PORT_UNUSED",
                altpll_component.port_extclk1 = "PORT_UNUSED",
                altpll_component.port_extclk2 = "PORT_UNUSED",
                altpll_component.port_extclk2 = "PORT_UNUSED",
                altpll_component.port_extclk3 = "PORT_UNUSED",
                altpll_component.port_extclk3 = "PORT_UNUSED",
                altpll_component.width_clock = 5;
                altpll_component.width_clock = 5;
 
 
 
 
endmodule
endmodule
 
 
// ============================================================
// ============================================================
// CNX file retrieval info
// CNX file retrieval info
// ============================================================
// ============================================================

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.