Line 24... |
Line 24... |
inclk0,
|
inclk0,
|
c0);
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c0);
|
|
|
parameter FREQ_MULT = 1;
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parameter FREQ_MULT = 1;
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parameter FREQ_DIV = 1;
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parameter FREQ_DIV = 1;
|
|
parameter FAMILY = "Cyclone III";
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|
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input inclk0;
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input inclk0;
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output c0;
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output c0;
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|
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wire [4:0] sub_wire0;
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wire [4:0] sub_wire0;
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Line 81... |
Line 82... |
altpll_component.clk0_duty_cycle = 50,
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altpll_component.clk0_duty_cycle = 50,
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altpll_component.clk0_multiply_by = FREQ_MULT,
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altpll_component.clk0_multiply_by = FREQ_MULT,
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altpll_component.clk0_phase_shift = "0",
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altpll_component.clk0_phase_shift = "0",
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altpll_component.compensate_clock = "CLK0",
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altpll_component.compensate_clock = "CLK0",
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altpll_component.inclk0_input_frequency = 20000,
|
altpll_component.inclk0_input_frequency = 20000,
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altpll_component.intended_device_family = "Cyclone III",
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altpll_component.intended_device_family = FAMILY,
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altpll_component.lpm_hint = "CBX_MODULE_PREFIX=minsocPll",
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altpll_component.lpm_hint = "CBX_MODULE_PREFIX=minsocPll",
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altpll_component.lpm_type = "altpll",
|
altpll_component.lpm_type = "altpll",
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altpll_component.operation_mode = "NORMAL",
|
altpll_component.operation_mode = "NORMAL",
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altpll_component.pll_type = "AUTO",
|
altpll_component.pll_type = "AUTO",
|
altpll_component.port_activeclock = "PORT_UNUSED",
|
altpll_component.port_activeclock = "PORT_UNUSED",
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Line 128... |
Line 129... |
altpll_component.port_extclk0 = "PORT_UNUSED",
|
altpll_component.port_extclk0 = "PORT_UNUSED",
|
altpll_component.port_extclk1 = "PORT_UNUSED",
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altpll_component.port_extclk1 = "PORT_UNUSED",
|
altpll_component.port_extclk2 = "PORT_UNUSED",
|
altpll_component.port_extclk2 = "PORT_UNUSED",
|
altpll_component.port_extclk3 = "PORT_UNUSED",
|
altpll_component.port_extclk3 = "PORT_UNUSED",
|
altpll_component.width_clock = 5;
|
altpll_component.width_clock = 5;
|
|
|
|
|
endmodule
|
endmodule
|
|
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// ============================================================
|
// ============================================================
|
// CNX file retrieval info
|
// CNX file retrieval info
|
// ============================================================
|
// ============================================================
|