//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Generic Wishbone controller for ////
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//// Generic Wishbone controller for ////
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//// Single-Port Synchronous RAM ////
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//// Single-Port Synchronous RAM ////
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//// ////
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//// ////
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//// This file is part of memory library available from ////
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//// This file is part of memory library available from ////
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//// http://www.opencores.org/cvsweb.shtml/minsoc/ ////
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//// http://www.opencores.org/cvsweb.shtml/minsoc/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// This Wishbone controller connects to the wrapper of ////
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//// This Wishbone controller connects to the wrapper of ////
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//// the single-port synchronous memory interface. ////
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//// the single-port synchronous memory interface. ////
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//// Besides universal memory due to onchip_ram it provides a ////
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//// Besides universal memory due to onchip_ram it provides a ////
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//// generic way to set the depth of the memory. ////
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//// generic way to set the depth of the memory. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Raul Fajardo, rfajardo@gmail.com ////
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//// - Raul Fajardo, rfajardo@gmail.com ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.gnu.org/licenses/lgpl.html ////
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//// from http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// Revision History
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// Revision History
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//
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//
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// Revision 1.1 2009/10/02 16:49 fajardo
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// Revision 1.1 2009/10/02 16:49 fajardo
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// Not using the oe signal (output enable) from
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// Not using the oe signal (output enable) from
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// memories, instead multiplexing the outputs
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// memories, instead multiplexing the outputs
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// between the different instantiated blocks
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// between the different instantiated blocks
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//
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//
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//
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//
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// Revision 1.0 2009/08/18 15:15:00 fajardo
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// Revision 1.0 2009/08/18 15:15:00 fajardo
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// Created interface and tested
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// Created interface and tested
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//
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//
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module minsoc_onchip_ram_top (
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module minsoc_onchip_ram_top (
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wb_clk_i, wb_rst_i,
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wb_clk_i, wb_rst_i,
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wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
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wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
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wb_stb_i, wb_ack_o, wb_err_o
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wb_stb_i, wb_ack_o, wb_err_o
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);
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);
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//
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//
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// Parameters
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// Parameters
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//
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//
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parameter adr_width = 13; //Memory address width, is composed by blocks of aw_int, is not allowed to be less than 12
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parameter adr_width = 13; //Memory address width, is composed by blocks of aw_int, is not allowed to be less than 12
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localparam aw_int = 11; //11 = 2048
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localparam aw_int = 11; //11 = 2048
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localparam blocks = (1<<(adr_width-aw_int)); //generated memory contains "blocks" memory blocks of 2048x32 2048 depth x32 bit data
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localparam blocks = (1<<(adr_width-aw_int)); //generated memory contains "blocks" memory blocks of 2048x32 2048 depth x32 bit data
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//
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//
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// I/O Ports
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// I/O Ports
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//
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//
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input wb_clk_i;
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input wb_clk_i;
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input wb_rst_i;
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input wb_rst_i;
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//
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//
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// WB slave i/f
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// WB slave i/f
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//
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//
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input [31:0] wb_dat_i;
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input [31:0] wb_dat_i;
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output [31:0] wb_dat_o;
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output [31:0] wb_dat_o;
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input [31:0] wb_adr_i;
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input [31:0] wb_adr_i;
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input [3:0] wb_sel_i;
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input [3:0] wb_sel_i;
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input wb_we_i;
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input wb_we_i;
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input wb_cyc_i;
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input wb_cyc_i;
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input wb_stb_i;
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input wb_stb_i;
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output wb_ack_o;
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output wb_ack_o;
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output wb_err_o;
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output wb_err_o;
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//
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//
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// Internal regs and wires
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// Internal regs and wires
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//
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//
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wire we;
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wire we;
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wire [3:0] be_i;
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wire [3:0] be_i;
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wire [31:0] wb_dat_o;
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wire [31:0] wb_dat_o;
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reg ack_we;
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reg ack_we;
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reg ack_re;
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reg ack_re;
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//
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//
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// Aliases and simple assignments
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// Aliases and simple assignments
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//
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//
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assign wb_ack_o = ack_re | ack_we;
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assign wb_ack_o = ack_re | ack_we;
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assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:adr_width+2]); // If Access to > (8-bit leading prefix ignored)
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assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:adr_width+2]); // If Access to > (8-bit leading prefix ignored)
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assign we = wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:0]);
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assign we = wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:0]);
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assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i;
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assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i;
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//
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//
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// Write acknowledge
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// Write acknowledge
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//
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//
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always @ (negedge wb_clk_i or posedge wb_rst_i)
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always @ (negedge wb_clk_i or posedge wb_rst_i)
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begin
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begin
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if (wb_rst_i)
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if (wb_rst_i)
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ack_we <= 1'b0;
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ack_we <= 1'b0;
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else
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else
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if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we)
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if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we)
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ack_we <= #1 1'b1;
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ack_we <= #1 1'b1;
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else
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else
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ack_we <= #1 1'b0;
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ack_we <= #1 1'b0;
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end
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end
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//
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//
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// read acknowledge
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// read acknowledge
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//
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//
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always @ (posedge wb_clk_i or posedge wb_rst_i)
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always @ (posedge wb_clk_i or posedge wb_rst_i)
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begin
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begin
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if (wb_rst_i)
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if (wb_rst_i)
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ack_re <= 1'b0;
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ack_re <= 1'b0;
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else
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else
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if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re)
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if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re)
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ack_re <= #1 1'b1;
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ack_re <= #1 1'b1;
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else
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else
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ack_re <= #1 1'b0;
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ack_re <= #1 1'b0;
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end
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end
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//Generic (multiple inputs x 1 output) MUX
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//Generic (multiple inputs x 1 output) MUX
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localparam mux_in_nr = blocks;
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localparam mux_in_nr = blocks;
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localparam slices = adr_width-aw_int;
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localparam slices = adr_width-aw_int;
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localparam mux_out_nr = blocks-1;
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localparam mux_out_nr = blocks-1;
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wire [31:0] int_dat_o[0:mux_in_nr-1];
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wire [31:0] int_dat_o[0:mux_in_nr-1];
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wire [31:0] mux_out[0:mux_out_nr-1];
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wire [31:0] mux_out[0:mux_out_nr-1];
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generate
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generate
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genvar j, k;
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genvar j, k;
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for (j=0; j<slices; j=j+1) begin : SLICES
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for (j=0; j<slices; j=j+1) begin : SLICES
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for (k=0; k<(mux_in_nr>>(j+1)); k=k+1) begin : MUX
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for (k=0; k<(mux_in_nr>>(j+1)); k=k+1) begin : MUX
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if (j==0) begin
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if (j==0) begin
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mux2 #
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mux2 #
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(
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(
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.dw(32)
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.dw(32)
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)
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)
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mux_int(
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mux_int(
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.sel( wb_adr_i[aw_int+2+j] ),
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.sel( wb_adr_i[aw_int+2+j] ),
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.in1( int_dat_o[k*2] ),
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.in1( int_dat_o[k*2] ),
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.in2( int_dat_o[k*2+1] ),
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.in2( int_dat_o[k*2+1] ),
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.out( mux_out[k] )
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.out( mux_out[k] )
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);
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);
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end
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end
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else begin
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else begin
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mux2 #
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mux2 #
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(
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(
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.dw(32)
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.dw(32)
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)
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)
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mux_int(
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mux_int(
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.sel( wb_adr_i[aw_int+2+j] ),
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.sel( wb_adr_i[aw_int+2+j] ),
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.in1( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2] ),
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.in1( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2] ),
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.in2( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2+1] ),
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.in2( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2+1] ),
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.out( mux_out[(mux_in_nr-(mux_in_nr>>j))+k] )
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.out( mux_out[(mux_in_nr-(mux_in_nr>>j))+k] )
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);
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);
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end
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end
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end
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end
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end
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end
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endgenerate
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endgenerate
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//last output = total output
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//last output = total output
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assign wb_dat_o = mux_out[mux_out_nr-1];
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assign wb_dat_o = mux_out[mux_out_nr-1];
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//(mux_in_nr-(mux_in_nr>>j)):
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//(mux_in_nr-(mux_in_nr>>j)):
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//-Given sum of 2^i | i = x -> y series can be resumed to 2^(y+1)-2^x
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//-Given sum of 2^i | i = x -> y series can be resumed to 2^(y+1)-2^x
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//so, with this expression I'm evaluating how many times the internal loop has been run
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//so, with this expression I'm evaluating how many times the internal loop has been run
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wire [blocks-1:0] bank;
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wire [blocks-1:0] bank;
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generate
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generate
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genvar i;
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genvar i;
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for (i=0; i < blocks; i=i+1) begin : MEM
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for (i=0; i < blocks; i=i+1) begin : MEM
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assign bank[i] = wb_adr_i[adr_width+1:aw_int+2] == i;
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assign bank[i] = wb_adr_i[adr_width+1:aw_int+2] == i;
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//BANK0
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//BANK0
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minsoc_onchip_ram block_ram_0 (
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minsoc_onchip_ram block_ram_0 (
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.clk(wb_clk_i),
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.clk(wb_clk_i),
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.rst(wb_rst_i),
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.rst(wb_rst_i),
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.addr(wb_adr_i[aw_int+1:2]),
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.addr(wb_adr_i[aw_int+1:2]),
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.di(wb_dat_i[7:0]),
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.di(wb_dat_i[7:0]),
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.doq(int_dat_o[i][7:0]),
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.doq(int_dat_o[i][7:0]),
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.we(we & bank[i]),
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.we(we & bank[i]),
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.oe(1'b1),
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.oe(1'b1),
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.ce(be_i[0])
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.ce(be_i[0])
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);
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);
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minsoc_onchip_ram block_ram_1 (
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minsoc_onchip_ram block_ram_1 (
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.clk(wb_clk_i),
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.clk(wb_clk_i),
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.rst(wb_rst_i),
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.rst(wb_rst_i),
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.addr(wb_adr_i[aw_int+1:2]),
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.addr(wb_adr_i[aw_int+1:2]),
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.di(wb_dat_i[15:8]),
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.di(wb_dat_i[15:8]),
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.doq(int_dat_o[i][15:8]),
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.doq(int_dat_o[i][15:8]),
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.we(we & bank[i]),
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.we(we & bank[i]),
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.oe(1'b1),
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.oe(1'b1),
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.ce(be_i[1])
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.ce(be_i[1])
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);
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);
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|
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minsoc_onchip_ram block_ram_2 (
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minsoc_onchip_ram block_ram_2 (
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.clk(wb_clk_i),
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.clk(wb_clk_i),
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.rst(wb_rst_i),
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.rst(wb_rst_i),
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.addr(wb_adr_i[aw_int+1:2]),
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.addr(wb_adr_i[aw_int+1:2]),
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.di(wb_dat_i[23:16]),
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.di(wb_dat_i[23:16]),
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.doq(int_dat_o[i][23:16]),
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.doq(int_dat_o[i][23:16]),
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.we(we & bank[i]),
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.we(we & bank[i]),
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.oe(1'b1),
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.oe(1'b1),
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.ce(be_i[2])
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.ce(be_i[2])
|
);
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);
|
|
|
minsoc_onchip_ram block_ram_3 (
|
minsoc_onchip_ram block_ram_3 (
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.clk(wb_clk_i),
|
.clk(wb_clk_i),
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.rst(wb_rst_i),
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.rst(wb_rst_i),
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.addr(wb_adr_i[aw_int+1:2]),
|
.addr(wb_adr_i[aw_int+1:2]),
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.di(wb_dat_i[31:24]),
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.di(wb_dat_i[31:24]),
|
.doq(int_dat_o[i][31:24]),
|
.doq(int_dat_o[i][31:24]),
|
.we(we & bank[i]),
|
.we(we & bank[i]),
|
.oe(1'b1),
|
.oe(1'b1),
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.ce(be_i[3])
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.ce(be_i[3])
|
);
|
);
|
|
|
end
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end
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endgenerate
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endgenerate
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|
|
endmodule
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endmodule
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|
|
module mux2(sel,in1,in2,out);
|
module mux2(sel,in1,in2,out);
|
|
|
parameter dw = 32;
|
parameter dw = 32;
|
|
|
input sel;
|
input sel;
|
input [dw-1:0] in1, in2;
|
input [dw-1:0] in1, in2;
|
output reg [dw-1:0] out;
|
output reg [dw-1:0] out;
|
|
|
always @ (sel or in1 or in2)
|
always @ (sel or in1 or in2)
|
begin
|
begin
|
case (sel)
|
case (sel)
|
1'b0: out = in1;
|
1'b0: out = in1;
|
1'b1: out = in2;
|
1'b1: out = in2;
|
endcase
|
endcase
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
