PROJECT_DIR=(backend bench/verilog bench/verilog/vpi bench/verilog/sim_lib rtl/verilog)
PROJECT_SRC=(minsoc_bench_defines.v
minsoc_bench.v
minsoc_memory_model.v
dbg_comm_vpi.v
fpga_memory_primitives.v
timescale.v)

<p>Error running this command: <code>diff -w -U 5 "/tmp/rbiTzM" ""</code></p><p>diff: : No such file or directory</p>