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https://opencores.org/ocsvn/minsoc/minsoc/trunk
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| Rev 17 |
Rev 18 |
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+incdir+../../rtl/verilog/uart16550/rtl/verilog
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+incdir+../../rtl/verilog/uart16550/rtl/verilog
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+incdir+../../rtl/verilog/ethmac/rtl/verilog
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+incdir+../../rtl/verilog/ethmac/rtl/verilog
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../../bench/verilog/minsoc_bench_defines.v
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../../bench/verilog/minsoc_bench_defines.v
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../../bench/verilog/minsoc_bench.v
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../../bench/verilog/minsoc_bench.v
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../../bench/verilog/minsoc_memory_model.v
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../../bench/verilog/minsoc_memory_model.v
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#../../bench/verilog/tb_eth_defines.v
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#../../bench/verilog/eth_phy_defines.v
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#../../bench/verilog/eth_phy.v
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../../bench/verilog/vpi/dbg_comm_vpi.v
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../../bench/verilog/vpi/dbg_comm_vpi.v
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../../bench/verilog/sim_lib/fpga_memory_primitives.v
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../../bench/verilog/sim_lib/fpga_memory_primitives.v
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../../rtl/verilog/minsoc_top.v
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../../rtl/verilog/minsoc_top.v
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../../rtl/verilog/minsoc_startup/spi_top.v
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../../rtl/verilog/minsoc_startup/spi_top.v
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../../rtl/verilog/minsoc_startup/spi_defines.v
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../../rtl/verilog/minsoc_startup/spi_defines.v
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