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module minsoc_wb_32_8_bridge(
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module minsoc_wb_32_8_bridge(
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wb_32_sel_i,
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wb_32_sel_i,
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wb_32_dat_i, wb_32_dat_o, wb_32_adr_i,
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wb_32_dat_i, wb_32_dat_o, wb_32_adr_i,
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wb_8_dat_i, wb_8_dat_o, wb_8_adr_i
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wb_8_dat_i, wb_8_dat_o, wb_8_adr_i
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);
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);
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input [3:0] wb_32_sel_i;
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input [3:0] wb_32_sel_i;
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input [31:0] wb_32_dat_i;
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input [31:0] wb_32_dat_i;
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output reg [31:0] wb_32_dat_o;
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output reg [31:0] wb_32_dat_o;
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input [31:0] wb_32_adr_i;
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input [31:0] wb_32_adr_i;
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output reg [7:0] wb_8_dat_i;
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output reg [7:0] wb_8_dat_i;
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input [7:0] wb_8_dat_o;
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input [7:0] wb_8_dat_o;
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output [31:0] wb_8_adr_i;
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output [31:0] wb_8_adr_i;
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reg [1:0] wb_8_adr;
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reg [1:0] wb_8_adr;
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// put output to the correct byte in 32 bits using select line
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// put output to the correct byte in 32 bits using select line
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always @(wb_32_sel_i or wb_8_dat_o)
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always @(wb_32_sel_i or wb_8_dat_o)
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case (wb_32_sel_i)
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case (wb_32_sel_i)
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4'b0001: wb_32_dat_o <= #1 {24'b0, wb_8_dat_o};
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4'b0001: wb_32_dat_o <= #1 {24'b0, wb_8_dat_o};
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4'b0010: wb_32_dat_o <= #1 {16'b0, wb_8_dat_o , 8'b0};
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4'b0010: wb_32_dat_o <= #1 {16'b0, wb_8_dat_o , 8'b0};
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4'b0100: wb_32_dat_o <= #1 {8'b0, wb_8_dat_o , 16'b0};
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4'b0100: wb_32_dat_o <= #1 {8'b0, wb_8_dat_o , 16'b0};
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4'b1000: wb_32_dat_o <= #1 {wb_8_dat_o , 24'b0};
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4'b1000: wb_32_dat_o <= #1 {wb_8_dat_o , 24'b0};
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4'b1111: wb_32_dat_o <= #1 {24'b0, wb_8_dat_o};
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4'b1111: wb_32_dat_o <= #1 {24'b0, wb_8_dat_o};
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default: wb_32_dat_o <= #1 0;
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default: wb_32_dat_o <= #1 0;
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endcase // case(wb_sel_i)
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endcase // case(wb_sel_i)
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always @(wb_32_sel_i or wb_32_dat_i)
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always @(wb_32_sel_i or wb_32_dat_i)
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begin
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begin
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case (wb_32_sel_i)
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case (wb_32_sel_i)
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4'b0001 : wb_8_dat_i = wb_32_dat_i[7:0];
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4'b0001 : wb_8_dat_i = wb_32_dat_i[7:0];
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4'b0010 : wb_8_dat_i = wb_32_dat_i[15:8];
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4'b0010 : wb_8_dat_i = wb_32_dat_i[15:8];
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4'b0100 : wb_8_dat_i = wb_32_dat_i[23:16];
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4'b0100 : wb_8_dat_i = wb_32_dat_i[23:16];
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4'b1000 : wb_8_dat_i = wb_32_dat_i[31:24];
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4'b1000 : wb_8_dat_i = wb_32_dat_i[31:24];
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default : wb_8_dat_i = wb_32_dat_i[7:0];
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default : wb_8_dat_i = wb_32_dat_i[7:0];
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endcase // case(wb_sel_i)
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endcase // case(wb_sel_i)
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case (wb_32_sel_i)
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case (wb_32_sel_i)
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4'b0001 : wb_8_adr = 2'h3;
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4'b0001 : wb_8_adr = 2'h3;
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4'b0010 : wb_8_adr = 2'h2;
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4'b0010 : wb_8_adr = 2'h2;
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4'b0100 : wb_8_adr = 2'h1;
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4'b0100 : wb_8_adr = 2'h1;
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4'b1000 : wb_8_adr = 2'h0;
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4'b1000 : wb_8_adr = 2'h0;
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default : wb_8_adr = 2'h0;
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default : wb_8_adr = 2'h0;
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endcase // case(wb_sel_i)
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endcase // case(wb_sel_i)
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end
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end
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assign wb_8_adr_i = { wb_32_adr_i[31:2] , wb_8_adr };
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assign wb_8_adr_i = { wb_32_adr_i[31:2] , wb_8_adr };
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endmodule
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endmodule
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