URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
[/] [minsoc/] [trunk/] [prj/] [src/] [minsoc_top.prj] - Diff between revs 89 and 158
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| Rev 89 |
Rev 158 |
PROJECT_DIR=(backend rtl/verilog rtl/verilog/minsoc_startup rtl/verilog/or1200/rtl/verilog rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog rtl/verilog/ethmac/rtl/verilog rtl/verilog/uart16550/rtl/verilog)
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PROJECT_DIR=(backend rtl/verilog rtl/verilog/minsoc_startup rtl/verilog/or1200/rtl/verilog rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog rtl/verilog/ethmac/rtl/verilog rtl/verilog/uart16550/rtl/verilog)
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PROJECT_SRC=(minsoc_defines.v
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PROJECT_SRC=(minsoc_defines.v
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timescale.v
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timescale.v
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interconnect_defines.v
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minsoc_top.v
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minsoc_top.v
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minsoc_tc_top.v
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minsoc_tc_top.v
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minsoc_onchip_ram.v
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minsoc_onchip_ram.v
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minsoc_onchip_ram_top.v
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minsoc_onchip_ram_top.v
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minsoc_clock_manager.v
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minsoc_clock_manager.v
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altera_pll.v
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altera_pll.v
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xilinx_dcm.v
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xilinx_dcm.v
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minsoc_xilinx_internal_jtag.v
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minsoc_xilinx_internal_jtag.v
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spi_top.v
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spi_top.v
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spi_defines.v
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spi_defines.v
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spi_shift.v
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spi_shift.v
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spi_clgen.v
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spi_clgen.v
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OR1K_startup_generic.v)
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OR1K_startup_generic.v)
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