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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [altera_pll.v] - Diff between revs 62 and 63

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Rev 62 Rev 63
Line 56... Line 56...
        wire [0:0] sub_wire1 = sub_wire0[0:0];
        wire [0:0] sub_wire1 = sub_wire0[0:0];
        wire  c0 = sub_wire1;
        wire  c0 = sub_wire1;
        wire  sub_wire2 = inclk0;
        wire  sub_wire2 = inclk0;
        wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
        wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
 
 
 
`ifdef ALTERA_FPGA
        altpll  altpll_component (
        altpll  altpll_component (
                                .inclk (sub_wire3),
                                .inclk (sub_wire3),
                                .clk (sub_wire0),
                                .clk (sub_wire0),
                                .activeclock (),
                                .activeclock (),
                                .areset (1'b0),
                                .areset (1'b0),
Line 149... Line 150...
                altpll_component.port_extclk0 = "PORT_UNUSED",
                altpll_component.port_extclk0 = "PORT_UNUSED",
                altpll_component.port_extclk1 = "PORT_UNUSED",
                altpll_component.port_extclk1 = "PORT_UNUSED",
                altpll_component.port_extclk2 = "PORT_UNUSED",
                altpll_component.port_extclk2 = "PORT_UNUSED",
                altpll_component.port_extclk3 = "PORT_UNUSED",
                altpll_component.port_extclk3 = "PORT_UNUSED",
                altpll_component.width_clock = 5;
                altpll_component.width_clock = 5;
 
`endif
 
 
endmodule
endmodule
 
 
 
 
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