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https://opencores.org/ocsvn/minsoc/minsoc/trunk
[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_clock_manager.v] - Diff between revs 52 and 56
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| Rev 52 |
Rev 56 |
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Line 7... |
);
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);
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//
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//
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// Parameters
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// Parameters
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//
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//
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parameter divisor = 5;
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parameter divisor = 2;
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parameter multiplier = 1;
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input clk_i;
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input clk_i;
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output clk_o;
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output clk_o;
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`ifdef NO_CLOCK_DIVISION
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`ifdef NO_CLOCK_DIVISION
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end
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end
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assign clk_o = clk_int;
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assign clk_o = clk_int;
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`elsif FPGA_CLOCK_DIVISION
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`elsif FPGA_CLOCK_DIVISION
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`ifdef ALTERA_FPGA
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`ifdef ALTERA_FPGA
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minsoc_pll
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`ifdef ARRIA_GX
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#(
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defparam systemPll.FAMILY = "Arria GX";
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multiplier,
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`elsif ARRIA_II_GX
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divisor
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defparam systemPll.FAMILY = "Arria II GX";
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)
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`elsif CYCLONE_I
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systemPll
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defparam systemPll.FAMILY = "Cyclone I";
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`elsif CYCLONE_II
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defparam systemPll.FAMILY = "Cyclone II";
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`elsif CYCLONE_III
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defparam systemPll.FAMILY = "Cyclone III";
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`elsif CYCLONE_III_LS
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defparam systemPll.FAMILY = "Cyclone III LS";
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`elsif CYCLONE_IV_E
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defparam systemPll.FAMILY = "Cyclone IV E";
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`elsif CYCLONE_IV_GS
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defparam systemPll.FAMILY = "Cyclone IV GS";
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`elsif MAX_II
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defparam systemPll.FAMILY = "MAX II";
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`elsif MAX_V
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defparam systemPll.FAMILY = "MAX V";
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`elsif MAX3000A
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defparam systemPll.FAMILY = "MAX3000A";
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`elsif MAX7000AE
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defparam systemPll.FAMILY = "MAX7000AE";
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`elsif MAX7000B
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defparam systemPll.FAMILY = "MAX7000B";
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`elsif MAX7000S
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defparam systemPll.FAMILY = "MAX7000S";
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`elsif STRATIX
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defparam systemPll.FAMILY = "Stratix";
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`elsif STRATIX_II
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defapram systemPll.FAMILY = "Stratix II";
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`elsif STRATIX_II_GX
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defparam systemPll.FAMILY = "Stratix II GX";
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`elsif STRATIX_III
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defparam systemPll.FAMILY = "Stratix III"
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`endif
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defparam systemPll.FREQ_DIV = divisor;
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minsoc_pll systemPll
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(
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(
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.inclk0(clk_i),
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.inclk0(clk_i),
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.c0(clk_o)
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.c0(clk_o)
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);
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);
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