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`include "minsoc_defines.v"
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`include "minsoc_defines.v"
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|
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module minsoc_clock_manager(
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module minsoc_clock_manager(
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clk_i,
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clk_i,
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clk_o
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clk_o
|
);
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);
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//
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//
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// Parameters
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// Parameters
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//
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//
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parameter divisor = 5;
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parameter divisor = 2;
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parameter multiplier = 1;
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|
|
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input clk_i;
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input clk_i;
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output clk_o;
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output clk_o;
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|
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`ifdef NO_CLOCK_DIVISION
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`ifdef NO_CLOCK_DIVISION
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assign clk_o = clk_i;
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assign clk_o = clk_i;
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|
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`elsif GENERIC_CLOCK_DIVISION
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`elsif GENERIC_CLOCK_DIVISION
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reg [31:0] clock_divisor;
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reg [31:0] clock_divisor;
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reg clk_int;
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reg clk_int;
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always @ (posedge clk_i)
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always @ (posedge clk_i)
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begin
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begin
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clock_divisor <= clock_divisor + 1'b1;
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clock_divisor <= clock_divisor + 1'b1;
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if ( clock_divisor >= divisor/2 - 1 ) begin
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if ( clock_divisor >= divisor/2 - 1 ) begin
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clk_int <= ~clk_int;
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clk_int <= ~clk_int;
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clock_divisor <= 32'h0000_0000;
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clock_divisor <= 32'h0000_0000;
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end
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end
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end
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end
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assign clk_o = clk_int;
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assign clk_o = clk_int;
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`elsif FPGA_CLOCK_DIVISION
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`elsif FPGA_CLOCK_DIVISION
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|
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`ifdef ALTERA_FPGA
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`ifdef ALTERA_FPGA
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minsoc_pll
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`ifdef ARRIA_GX
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#(
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defparam systemPll.FAMILY = "Arria GX";
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multiplier,
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`elsif ARRIA_II_GX
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divisor
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defparam systemPll.FAMILY = "Arria II GX";
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)
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`elsif CYCLONE_I
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systemPll
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defparam systemPll.FAMILY = "Cyclone I";
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`elsif CYCLONE_II
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defparam systemPll.FAMILY = "Cyclone II";
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`elsif CYCLONE_III
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defparam systemPll.FAMILY = "Cyclone III";
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`elsif CYCLONE_III_LS
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defparam systemPll.FAMILY = "Cyclone III LS";
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`elsif CYCLONE_IV_E
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defparam systemPll.FAMILY = "Cyclone IV E";
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`elsif CYCLONE_IV_GS
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defparam systemPll.FAMILY = "Cyclone IV GS";
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`elsif MAX_II
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defparam systemPll.FAMILY = "MAX II";
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`elsif MAX_V
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defparam systemPll.FAMILY = "MAX V";
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`elsif MAX3000A
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defparam systemPll.FAMILY = "MAX3000A";
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`elsif MAX7000AE
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defparam systemPll.FAMILY = "MAX7000AE";
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`elsif MAX7000B
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defparam systemPll.FAMILY = "MAX7000B";
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`elsif MAX7000S
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defparam systemPll.FAMILY = "MAX7000S";
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`elsif STRATIX
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defparam systemPll.FAMILY = "Stratix";
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`elsif STRATIX_II
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defapram systemPll.FAMILY = "Stratix II";
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`elsif STRATIX_II_GX
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defparam systemPll.FAMILY = "Stratix II GX";
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`elsif STRATIX_III
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defparam systemPll.FAMILY = "Stratix III"
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`endif
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defparam systemPll.FREQ_DIV = divisor;
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|
|
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minsoc_pll systemPll
|
(
|
(
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.inclk0(clk_i),
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.inclk0(clk_i),
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.c0(clk_o)
|
.c0(clk_o)
|
);
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);
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|
|
`elsif XILINX_FPGA
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`elsif XILINX_FPGA
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|
|
`ifdef SPARTAN2
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`ifdef SPARTAN2
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`define MINSOC_DLL
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`define MINSOC_DLL
|
`elsif VIRTEX
|
`elsif VIRTEX
|
`define MINSOC_DLL
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`define MINSOC_DLL
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`endif // !SPARTAN2/VIRTEX
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`endif // !SPARTAN2/VIRTEX
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|
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`ifdef SPARTAN3
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`ifdef SPARTAN3
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`define MINSOC_DCM
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`define MINSOC_DCM
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`elsif VIRTEX2
|
`elsif VIRTEX2
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`define MINSOC_DCM
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`define MINSOC_DCM
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`endif // !SPARTAN3/VIRTEX2
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`endif // !SPARTAN3/VIRTEX2
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|
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`ifdef SPARTAN3E
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`ifdef SPARTAN3E
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`define MINSOC_DCM_SP
|
`define MINSOC_DCM_SP
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`elsif SPARTAN3A
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`elsif SPARTAN3A
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`define MINSOC_DCM_SP
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`define MINSOC_DCM_SP
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`endif // !SPARTAN3E/SPARTAN3A
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`endif // !SPARTAN3E/SPARTAN3A
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|
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`ifdef VIRTEX4
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`ifdef VIRTEX4
|
`define MINSOC_DCM_ADV
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`define MINSOC_DCM_ADV
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`define MINSOC_DCM_COMPONENT "VIRTEX4"
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`define MINSOC_DCM_COMPONENT "VIRTEX4"
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`elsif VIRTEX5
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`elsif VIRTEX5
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`define MINSOC_DCM_ADV
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`define MINSOC_DCM_ADV
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`define MINSOC_DCM_COMPONENT "VIRTEX5"
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`define MINSOC_DCM_COMPONENT "VIRTEX5"
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`endif // !VIRTEX4/VIRTEX5
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`endif // !VIRTEX4/VIRTEX5
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|
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wire CLKIN_IN;
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wire CLKIN_IN;
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wire CLKDV_OUT;
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wire CLKDV_OUT;
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|
|
assign CLKIN_IN = clk_i;
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assign CLKIN_IN = clk_i;
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assign clk_o = CLKDV_OUT;
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assign clk_o = CLKDV_OUT;
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|
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wire CLKIN_IBUFG;
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wire CLKIN_IBUFG;
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wire CLK0_BUF;
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wire CLK0_BUF;
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wire CLKFB_IN;
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wire CLKFB_IN;
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wire CLKDV_BUF;
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wire CLKDV_BUF;
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|
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IBUFG CLKIN_IBUFG_INST (
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IBUFG CLKIN_IBUFG_INST (
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.I(CLKIN_IN),
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.I(CLKIN_IN),
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.O(CLKIN_IBUFG)
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.O(CLKIN_IBUFG)
|
);
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);
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|
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BUFG CLK0_BUFG_INST (
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BUFG CLK0_BUFG_INST (
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.I(CLK0_BUF),
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.I(CLK0_BUF),
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.O(CLKFB_IN)
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.O(CLKFB_IN)
|
);
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);
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|
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BUFG CLKDV_BUFG_INST (
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BUFG CLKDV_BUFG_INST (
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.I(CLKDV_BUF),
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.I(CLKDV_BUF),
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.O(CLKDV_OUT)
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.O(CLKDV_OUT)
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);
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);
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`ifdef MINSOC_DLL
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`ifdef MINSOC_DLL
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CLKDLL #(
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CLKDLL #(
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.CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,4.0,5.0,8.0 or 16.0
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.CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,4.0,5.0,8.0 or 16.0
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.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
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.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
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.FACTORY_JF(16'hC080), // FACTORY JF Values
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.FACTORY_JF(16'hC080), // FACTORY JF Values
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.STARTUP_WAIT("FALSE") // Delay config DONE until DLL LOCK, TRUE/FALSE
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.STARTUP_WAIT("FALSE") // Delay config DONE until DLL LOCK, TRUE/FALSE
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) CLKDLL_inst (
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) CLKDLL_inst (
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.CLK0(CLK0_BUF), // 0 degree DLL CLK output
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.CLK0(CLK0_BUF), // 0 degree DLL CLK output
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.CLK180(), // 180 degree DLL CLK output
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.CLK180(), // 180 degree DLL CLK output
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.CLK270(), // 270 degree DLL CLK output
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.CLK270(), // 270 degree DLL CLK output
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.CLK2X(), // 2X DLL CLK output
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.CLK2X(), // 2X DLL CLK output
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.CLK90(), // 90 degree DLL CLK output
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.CLK90(), // 90 degree DLL CLK output
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.CLKDV(CLKDV_BUF), // Divided DLL CLK out (CLKDV_DIVIDE)
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.CLKDV(CLKDV_BUF), // Divided DLL CLK out (CLKDV_DIVIDE)
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.LOCKED(), // DLL LOCK status output
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.LOCKED(), // DLL LOCK status output
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.CLKFB(CLKFB_IN), // DLL clock feedback
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.CLKFB(CLKFB_IN), // DLL clock feedback
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.CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DLL)
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.CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DLL)
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.RST(1'b0) // DLL asynchronous reset input
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.RST(1'b0) // DLL asynchronous reset input
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);
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);
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`elsif MINSOC_DCM
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`elsif MINSOC_DCM
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|
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DCM #(
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DCM #(
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.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
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.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
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.CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
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.CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
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// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
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// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
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.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
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.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
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.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
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.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
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.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
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.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
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.CLKIN_PERIOD(0.0), // Specify period of input clock
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.CLKIN_PERIOD(0.0), // Specify period of input clock
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.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
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.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
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.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
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.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
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.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
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.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
|
// an integer from 0 to 15
|
// an integer from 0 to 15
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.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
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.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
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.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
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.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
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.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
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.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
|
.FACTORY_JF(16'hC080), // FACTORY JF values
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.FACTORY_JF(16'hC080), // FACTORY JF values
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.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
|
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
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.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
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.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
|
) DCM_inst (
|
) DCM_inst (
|
.CLK0(CLK0_BUF), // 0 degree DCM CLK output
|
.CLK0(CLK0_BUF), // 0 degree DCM CLK output
|
.CLK180(), // 180 degree DCM CLK output
|
.CLK180(), // 180 degree DCM CLK output
|
.CLK270(), // 270 degree DCM CLK output
|
.CLK270(), // 270 degree DCM CLK output
|
.CLK2X(), // 2X DCM CLK output
|
.CLK2X(), // 2X DCM CLK output
|
.CLK2X180(), // 2X, 180 degree DCM CLK out
|
.CLK2X180(), // 2X, 180 degree DCM CLK out
|
.CLK90(), // 90 degree DCM CLK output
|
.CLK90(), // 90 degree DCM CLK output
|
.CLKDV(CLKDV_BUF), // Divided DCM CLK out (CLKDV_DIVIDE)
|
.CLKDV(CLKDV_BUF), // Divided DCM CLK out (CLKDV_DIVIDE)
|
.CLKFX(), // DCM CLK synthesis out (M/D)
|
.CLKFX(), // DCM CLK synthesis out (M/D)
|
.CLKFX180(), // 180 degree CLK synthesis out
|
.CLKFX180(), // 180 degree CLK synthesis out
|
.LOCKED(), // DCM LOCK status output
|
.LOCKED(), // DCM LOCK status output
|
.PSDONE(), // Dynamic phase adjust done output
|
.PSDONE(), // Dynamic phase adjust done output
|
.STATUS(), // 8-bit DCM status bits output
|
.STATUS(), // 8-bit DCM status bits output
|
.CLKFB(CLKFB_IN), // DCM clock feedback
|
.CLKFB(CLKFB_IN), // DCM clock feedback
|
.CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DCM)
|
.CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DCM)
|
.PSCLK(1'b0), // Dynamic phase adjust clock input
|
.PSCLK(1'b0), // Dynamic phase adjust clock input
|
.PSEN(1'b0), // Dynamic phase adjust enable input
|
.PSEN(1'b0), // Dynamic phase adjust enable input
|
.PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement
|
.PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement
|
.RST(1'b0) // DCM asynchronous reset input
|
.RST(1'b0) // DCM asynchronous reset input
|
);
|
);
|
|
|
`elsif MINSOC_DCM_SP
|
`elsif MINSOC_DCM_SP
|
|
|
DCM_SP #(
|
DCM_SP #(
|
.CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
|
.CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
|
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
|
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
|
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
|
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
|
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
|
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
|
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
|
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
|
.CLKIN_PERIOD(0.0), // Specify period of input clock
|
.CLKIN_PERIOD(0.0), // Specify period of input clock
|
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
|
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
|
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
|
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
|
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
|
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
|
// an integer from 0 to 15
|
// an integer from 0 to 15
|
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
|
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
|
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
|
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
|
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
|
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
|
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
|
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
|
) DCM_SP_inst (
|
) DCM_SP_inst (
|
.CLK0(CLK0_BUF), // 0 degree DCM CLK output
|
.CLK0(CLK0_BUF), // 0 degree DCM CLK output
|
.CLK180(), // 180 degree DCM CLK output
|
.CLK180(), // 180 degree DCM CLK output
|
.CLK270(), // 270 degree DCM CLK output
|
.CLK270(), // 270 degree DCM CLK output
|
.CLK2X(), // 2X DCM CLK output
|
.CLK2X(), // 2X DCM CLK output
|
.CLK2X180(), // 2X, 180 degree DCM CLK out
|
.CLK2X180(), // 2X, 180 degree DCM CLK out
|
.CLK90(), // 90 degree DCM CLK output
|
.CLK90(), // 90 degree DCM CLK output
|
.CLKDV(CLKDV_BUF), // Divided DCM CLK out (CLKDV_DIVIDE)
|
.CLKDV(CLKDV_BUF), // Divided DCM CLK out (CLKDV_DIVIDE)
|
.CLKFX(), // DCM CLK synthesis out (M/D)
|
.CLKFX(), // DCM CLK synthesis out (M/D)
|
.CLKFX180(), // 180 degree CLK synthesis out
|
.CLKFX180(), // 180 degree CLK synthesis out
|
.LOCKED(), // DCM LOCK status output
|
.LOCKED(), // DCM LOCK status output
|
.PSDONE(), // Dynamic phase adjust done output
|
.PSDONE(), // Dynamic phase adjust done output
|
.STATUS(), // 8-bit DCM status bits output
|
.STATUS(), // 8-bit DCM status bits output
|
.CLKFB(CLKFB_IN), // DCM clock feedback
|
.CLKFB(CLKFB_IN), // DCM clock feedback
|
.CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DCM)
|
.CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DCM)
|
.PSCLK(1'b0), // Dynamic phase adjust clock input
|
.PSCLK(1'b0), // Dynamic phase adjust clock input
|
.PSEN(1'b0), // Dynamic phase adjust enable input
|
.PSEN(1'b0), // Dynamic phase adjust enable input
|
.PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement
|
.PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement
|
.RST(1'b0) // DCM asynchronous reset input
|
.RST(1'b0) // DCM asynchronous reset input
|
);
|
);
|
|
|
`elsif MINSOC_DCM_ADV
|
`elsif MINSOC_DCM_ADV
|
|
|
DCM_ADV #(
|
DCM_ADV #(
|
.CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
|
.CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
|
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
|
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
|
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
|
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
|
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
|
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
|
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
|
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
|
.CLKIN_PERIOD(10.0), // Specify period of input clock in ns from 1.25 to 1000.00
|
.CLKIN_PERIOD(10.0), // Specify period of input clock in ns from 1.25 to 1000.00
|
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift mode of NONE, FIXED,
|
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift mode of NONE, FIXED,
|
// VARIABLE_POSITIVE, VARIABLE_CENTER or DIRECT
|
// VARIABLE_POSITIVE, VARIABLE_CENTER or DIRECT
|
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
|
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
|
.DCM_AUTOCALIBRATION("TRUE"), // DCM calibration circuitry "TRUE"/"FALSE"
|
.DCM_AUTOCALIBRATION("TRUE"), // DCM calibration circuitry "TRUE"/"FALSE"
|
.DCM_PERFORMANCE_MODE("MAX_SPEED"), // Can be MAX_SPEED or MAX_RANGE
|
.DCM_PERFORMANCE_MODE("MAX_SPEED"), // Can be MAX_SPEED or MAX_RANGE
|
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
|
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
|
// an integer from 0 to 15
|
// an integer from 0 to 15
|
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
|
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
|
.DLL_FREQUENCY_MODE("LOW"), // LOW, HIGH, or HIGH_SER frequency mode for DLL
|
.DLL_FREQUENCY_MODE("LOW"), // LOW, HIGH, or HIGH_SER frequency mode for DLL
|
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, "TRUE"/"FALSE"
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.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, "TRUE"/"FALSE"
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.FACTORY_JF(16'hf0f0), // FACTORY JF value suggested to be set to 16’hf0f0
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.FACTORY_JF(16'hf0f0), // FACTORY JF value suggested to be set to 16’hf0f0
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.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 1023
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.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 1023
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.SIM_DEVICE(`MINSOC_DCM_COMPONENT), // Set target device, "VIRTEX4" or "VIRTEX5"
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.SIM_DEVICE(`MINSOC_DCM_COMPONENT), // Set target device, "VIRTEX4" or "VIRTEX5"
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.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, "TRUE"/"FALSE"
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.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, "TRUE"/"FALSE"
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) DCM_ADV_inst (
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) DCM_ADV_inst (
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.CLK0(CLK0_BUF), // 0 degree DCM CLK output
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.CLK0(CLK0_BUF), // 0 degree DCM CLK output
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.CLK180(), // 180 degree DCM CLK output
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.CLK180(), // 180 degree DCM CLK output
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.CLK270(), // 270 degree DCM CLK output
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.CLK270(), // 270 degree DCM CLK output
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.CLK2X(), // 2X DCM CLK output
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.CLK2X(), // 2X DCM CLK output
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.CLK2X180(), // 2X, 180 degree DCM CLK out
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.CLK2X180(), // 2X, 180 degree DCM CLK out
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.CLK90(), // 90 degree DCM CLK output
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.CLK90(), // 90 degree DCM CLK output
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.CLKDV(CLKDV_BUF), // Divided DCM CLK out (CLKDV_DIVIDE)
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.CLKDV(CLKDV_BUF), // Divided DCM CLK out (CLKDV_DIVIDE)
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.CLKFX(), // DCM CLK synthesis out (M/D)
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.CLKFX(), // DCM CLK synthesis out (M/D)
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.CLKFX180(), // 180 degree CLK synthesis out
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.CLKFX180(), // 180 degree CLK synthesis out
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.DO(), // 16-bit data output for Dynamic Reconfiguration Port (DRP)
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.DO(), // 16-bit data output for Dynamic Reconfiguration Port (DRP)
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.DRDY(), // Ready output signal from the DRP
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.DRDY(), // Ready output signal from the DRP
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.LOCKED(), // DCM LOCK status output
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.LOCKED(), // DCM LOCK status output
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.PSDONE(), // Dynamic phase adjust done output
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.PSDONE(), // Dynamic phase adjust done output
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.CLKFB(CLKFB_IN), // DCM clock feedback
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.CLKFB(CLKFB_IN), // DCM clock feedback
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.CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DCM)
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.CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DCM)
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.DADDR(7'h00), // 7-bit address for the DRP
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.DADDR(7'h00), // 7-bit address for the DRP
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.DCLK(1'b0), // Clock for the DRP
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.DCLK(1'b0), // Clock for the DRP
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.DEN(1'b0), // Enable input for the DRP
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.DEN(1'b0), // Enable input for the DRP
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.DI(16'h0000), // 16-bit data input for the DRP
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.DI(16'h0000), // 16-bit data input for the DRP
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.DWE(1'b0), // Active high allows for writing configuration memory
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.DWE(1'b0), // Active high allows for writing configuration memory
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.PSCLK(1'b0), // Dynamic phase adjust clock input
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.PSCLK(1'b0), // Dynamic phase adjust clock input
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.PSEN(1'b0), // Dynamic phase adjust enable input
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.PSEN(1'b0), // Dynamic phase adjust enable input
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.PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement
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.PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement
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.RST(1'b0) // DCM asynchronous reset input
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.RST(1'b0) // DCM asynchronous reset input
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);
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);
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|
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`endif // !MINSOC_DLL/MINSOC_DCM/MINSOC_DCM_SP/MINSOC_DCM_ADV
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`endif // !MINSOC_DLL/MINSOC_DCM/MINSOC_DCM_SP/MINSOC_DCM_ADV
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`endif // !ALTERA_FPGA/XILINX_FPGA
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`endif // !ALTERA_FPGA/XILINX_FPGA
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`endif // !NO_CLOCK_DIVISION/GENERIC_CLOCK_DIVISION/FPGA_CLOCK_DIVISION
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`endif // !NO_CLOCK_DIVISION/GENERIC_CLOCK_DIVISION/FPGA_CLOCK_DIVISION
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endmodule
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endmodule
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