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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_top.v] - Diff between revs 75 and 156

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Rev 75 Rev 156
Line 418... Line 418...
      .update_dr_i ( update_dr ),
      .update_dr_i ( update_dr ),
 
 
      .debug_select_i( debug_select ),
      .debug_select_i( debug_select ),
        // WISHBONE common
        // WISHBONE common
      .wb_clk_i   ( wb_clk ),
      .wb_clk_i   ( wb_clk ),
 
      .wb_rst_i   ( wb_rst ),
 
 
      // WISHBONE master interface
      // WISHBONE master interface
      .wb_adr_o  ( wb_dm_adr_o ),
      .wb_adr_o  ( wb_dm_adr_o ),
      .wb_dat_i  ( wb_dm_dat_i ),
      .wb_dat_i  ( wb_dm_dat_i ),
      .wb_dat_o  ( wb_dm_dat_o ),
      .wb_dat_o  ( wb_dm_dat_o ),
Line 437... Line 438...
      // RISC signals
      // RISC signals
      .cpu0_clk_i  ( wb_clk ),
      .cpu0_clk_i  ( wb_clk ),
      .cpu0_addr_o ( dbg_adr ),
      .cpu0_addr_o ( dbg_adr ),
      .cpu0_data_i ( dbg_dat_risc ),
      .cpu0_data_i ( dbg_dat_risc ),
      .cpu0_data_o ( dbg_dat_dbg ),
      .cpu0_data_o ( dbg_dat_dbg ),
      .cpu0_bp_i   ( dbg_bp ),
      .cpu0_bp_i   ( (dbg_bp | (| dbg_wp[10:0])) ),
      .cpu0_stall_o( dbg_stall ),
      .cpu0_stall_o( dbg_stall ),
      .cpu0_stb_o  ( dbg_stb ),
      .cpu0_stb_o  ( dbg_stb ),
      .cpu0_we_o   ( dbg_we ),
      .cpu0_we_o   ( dbg_we ),
      .cpu0_ack_i  ( dbg_ack ),
      .cpu0_ack_i  ( dbg_ack ),
      .cpu0_rst_o  ( )
      .cpu0_rst_o  ( )

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