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https://opencores.org/ocsvn/minsoc/minsoc/trunk
[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_top.v] - Diff between revs 75 and 156
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| Rev 75 |
Rev 156 |
| Line 418... |
Line 418... |
.update_dr_i ( update_dr ),
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.update_dr_i ( update_dr ),
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.debug_select_i( debug_select ),
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.debug_select_i( debug_select ),
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// WISHBONE common
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// WISHBONE common
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.wb_clk_i ( wb_clk ),
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.wb_clk_i ( wb_clk ),
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.wb_rst_i ( wb_rst ),
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// WISHBONE master interface
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// WISHBONE master interface
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.wb_adr_o ( wb_dm_adr_o ),
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.wb_adr_o ( wb_dm_adr_o ),
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.wb_dat_i ( wb_dm_dat_i ),
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.wb_dat_i ( wb_dm_dat_i ),
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.wb_dat_o ( wb_dm_dat_o ),
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.wb_dat_o ( wb_dm_dat_o ),
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| Line 437... |
Line 438... |
// RISC signals
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// RISC signals
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.cpu0_clk_i ( wb_clk ),
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.cpu0_clk_i ( wb_clk ),
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.cpu0_addr_o ( dbg_adr ),
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.cpu0_addr_o ( dbg_adr ),
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.cpu0_data_i ( dbg_dat_risc ),
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.cpu0_data_i ( dbg_dat_risc ),
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.cpu0_data_o ( dbg_dat_dbg ),
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.cpu0_data_o ( dbg_dat_dbg ),
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.cpu0_bp_i ( dbg_bp ),
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.cpu0_bp_i ( (dbg_bp | (| dbg_wp[10:0])) ),
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.cpu0_stall_o( dbg_stall ),
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.cpu0_stall_o( dbg_stall ),
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.cpu0_stb_o ( dbg_stb ),
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.cpu0_stb_o ( dbg_stb ),
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.cpu0_we_o ( dbg_we ),
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.cpu0_we_o ( dbg_we ),
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.cpu0_ack_i ( dbg_ack ),
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.cpu0_ack_i ( dbg_ack ),
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.cpu0_rst_o ( )
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.cpu0_rst_o ( )
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