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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_top.v] - Diff between revs 17 and 20

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Rev 17 Rev 20
Line 125... Line 125...
wire    [31:0]           dbg_dat_dbg;
wire    [31:0]           dbg_dat_dbg;
wire    [31:0]           dbg_dat_risc;
wire    [31:0]           dbg_dat_risc;
wire    [31:0]           dbg_adr;
wire    [31:0]           dbg_adr;
wire                    dbg_ewt;
wire                    dbg_ewt;
wire                    dbg_stall;
wire                    dbg_stall;
wire    [2:0]            dbg_op;     //dbg_op[0] = dbg_we //dbg_op[2] = dbg_stb  (didn't change for backward compatibility with DBG_IF_MODEL
wire            dbg_we;
 
wire            dbg_stb;
wire                    dbg_ack;
wire                    dbg_ack;
 
 
//
//
// RISC instruction master i/f wires
// RISC instruction master i/f wires
//
//
Line 435... Line 436...
      .cpu0_addr_o ( dbg_adr ),
      .cpu0_addr_o ( dbg_adr ),
      .cpu0_data_i ( dbg_dat_risc ),
      .cpu0_data_i ( dbg_dat_risc ),
      .cpu0_data_o ( dbg_dat_dbg ),
      .cpu0_data_o ( dbg_dat_dbg ),
      .cpu0_bp_i   ( dbg_bp ),
      .cpu0_bp_i   ( dbg_bp ),
      .cpu0_stall_o( dbg_stall ),
      .cpu0_stall_o( dbg_stall ),
      .cpu0_stb_o  ( dbg_op[2] ),
      .cpu0_stb_o  ( dbg_stb ),
      .cpu0_we_o   ( dbg_op[0] ),
      .cpu0_we_o   ( dbg_we ),
      .cpu0_ack_i  ( dbg_ack ),
      .cpu0_ack_i  ( dbg_ack ),
      .cpu0_rst_o  ( )
      .cpu0_rst_o  ( )
 
 
);
);
 
 
Line 567... Line 568...
        .dbg_is_o       ( dbg_is ),
        .dbg_is_o       ( dbg_is ),
        .dbg_wp_o       ( dbg_wp ),
        .dbg_wp_o       ( dbg_wp ),
        .dbg_bp_o       ( dbg_bp ),
        .dbg_bp_o       ( dbg_bp ),
        .dbg_dat_o      ( dbg_dat_risc ),
        .dbg_dat_o      ( dbg_dat_risc ),
        .dbg_ack_o      ( dbg_ack ),
        .dbg_ack_o      ( dbg_ack ),
        .dbg_stb_i      ( dbg_op[2] ),
        .dbg_stb_i      ( dbg_stb ),
        .dbg_we_i       ( dbg_op[0] ),
        .dbg_we_i       ( dbg_we ),
 
 
        // Power Management
        // Power Management
        .pm_clksd_o     ( ),
        .pm_clksd_o     ( ),
        .pm_cpustall_i  ( 1'b0 ),
        .pm_cpustall_i  ( 1'b0 ),
        .pm_dc_gate_o   ( ),
        .pm_dc_gate_o   ( ),

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