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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [xilinx_dcm.v] - Diff between revs 62 and 88
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| Rev 62 |
Rev 88 |
| Line 51... |
Line 51... |
wire CLKIN_IBUFG;
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wire CLKIN_IBUFG;
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wire CLK0_BUF;
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wire CLK0_BUF;
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wire CLKFB_IN;
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wire CLKFB_IN;
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wire CLKDV_BUF;
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wire CLKDV_BUF;
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`ifdef XILINX_FPGA
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IBUFG CLKIN_IBUFG_INST (
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IBUFG CLKIN_IBUFG_INST (
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.I(CLKIN_IN),
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.I(CLKIN_IN),
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.O(CLKIN_IBUFG)
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.O(CLKIN_IBUFG)
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);
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);
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| Line 216... |
Line 218... |
.PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement
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.PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement
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.RST(1'b0) // DCM asynchronous reset input
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.RST(1'b0) // DCM asynchronous reset input
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);
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);
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`endif // !XILINX_DLL/XILINX_DCM/XILINX_DCM_SP/XILINX_DCM_ADV
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`endif // !XILINX_DLL/XILINX_DCM/XILINX_DCM_SP/XILINX_DCM_ADV
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`endif // !XILINX_FPGA
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endmodule
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endmodule
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