URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [utils/] [contributions/] [minsoc_tc_top_B3.v] - Diff between revs 40 and 164

Rev 40	Rev 164
Line 85...	Line 85...

`//`	`//`
`// Width of WB initiator inputs (coming from WB masters)`	`// Width of WB initiator inputs (coming from WB masters)`
`//`	`//`
`// cyc + stb + address bus width +`	`// cyc + stb + address bus width +`
`// byte select bus width + we + data bus width`	`// byte select bus width + we + data bus width + cti + bte`
`//`	`//`
`define TC_IIN_W 1+1+1+`TC_AW+`TC_BSW+1+`TC_DW	`define TC_IIN_W 1+1+`TC_AW+`TC_BSW+1+`TC_DW+3+2

`//`	`//`
`// Traffic Cop Top`	`// Traffic Cop Top`
`//`	`//`
`module minsoc_tc_top (`	`module minsoc_tc_top (`
Line 1031...	Line 1031...
`.t7_wb_dat_o(t8_wb_dat_o),`	`.t7_wb_dat_o(t8_wb_dat_o),`
`.t7_wb_dat_i(t8_wb_dat_i),`	`.t7_wb_dat_i(t8_wb_dat_i),`
`.t7_wb_ack_i(t8_wb_ack_i),`	`.t7_wb_ack_i(t8_wb_ack_i),`
`.t7_wb_err_i(t8_wb_err_i),`	`.t7_wb_err_i(t8_wb_err_i),`
`.t7_wb_cti_o(t8_wb_cti_o),`	`.t7_wb_cti_o(t8_wb_cti_o),`
`.t7_wb_bte_o(t8_wb_bte_o),`	`.t7_wb_bte_o(t8_wb_bte_o)`


`);`	`);`

`endmodule`	`endmodule`