------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------
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--
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--
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-- Geoffrey Ottoy - DraMCo research group
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-- Geoffrey Ottoy - DraMCo research group
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--
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--
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-- Module Name: x_shift_reg.vhd / entity x_shift_reg
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-- Module Name: x_shift_reg.vhd / entity x_shift_reg
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--
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--
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-- Last Modified: 18/06/2012
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-- Last Modified: 18/06/2012
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--
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--
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-- Description: n-bit shift register with lsb output
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-- Description: n-bit shift register with lsb output
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--
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--
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--
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--
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-- Dependencies: none
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-- Dependencies: none
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 1.00 - Architecture
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-- Revision 1.00 - Architecture
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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--
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--
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--
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--
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------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------
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--
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--
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-- NOTICE:
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-- NOTICE:
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--
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--
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-- Copyright DraMCo research group. 2011. This code may be contain portions patented
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-- Copyright DraMCo research group. 2011. This code may be contain portions patented
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-- by other third parties!
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-- by other third parties!
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--
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--
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------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity x_shift_reg is
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entity x_shift_reg is
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generic( n : integer := 1536;
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generic( n : integer := 1536;
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t : integer := 48;
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t : integer := 48;
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tl : integer := 16
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tl : integer := 16
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);
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);
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port( clk : in STD_LOGIC;
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port( clk : in STD_LOGIC;
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reset : in STD_LOGIC;
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reset : in STD_LOGIC;
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x_in : in STD_LOGIC_VECTOR((n-1) downto 0);
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x_in : in STD_LOGIC_VECTOR((n-1) downto 0);
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load_x : in STD_LOGIC;
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load_x : in STD_LOGIC;
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next_x : in STD_LOGIC;
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next_x : in STD_LOGIC;
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p_sel : in STD_LOGIC_VECTOR(1 downto 0);
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p_sel : in STD_LOGIC_VECTOR(1 downto 0);
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x_i : out STD_LOGIC
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x_i : out STD_LOGIC
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);
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);
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end x_shift_reg;
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end x_shift_reg;
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architecture Behavioral of x_shift_reg is
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architecture Behavioral of x_shift_reg is
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signal x_reg_i : std_logic_vector((n-1) downto 0); -- register
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signal x_reg_i : std_logic_vector((n-1) downto 0); -- register
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constant s : integer := n/t; -- nr of stages
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constant s : integer := n/t; -- nr of stages
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constant offset : integer := s*tl; -- calculate startbit pos of higher part of pipeline
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constant offset : integer := s*tl; -- calculate startbit pos of higher part of pipeline
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begin
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begin
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REG_PROC: process(reset, clk)
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REG_PROC: process(reset, clk)
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begin
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begin
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if reset = '1' then -- Reset, clear the register
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if reset = '1' then -- Reset, clear the register
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x_reg_i <= (others => '0');
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x_reg_i <= (others => '0');
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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if load_x = '1' then -- Load_x, load the register with x_in
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if load_x = '1' then -- Load_x, load the register with x_in
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x_reg_i <= x_in;
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x_reg_i <= x_in;
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elsif next_x = '1' then -- next_x, shift to right. LSbit gets lost and zero's are shifted in
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elsif next_x = '1' then -- next_x, shift to right. LSbit gets lost and zero's are shifted in
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x_reg_i((n-2) downto 0) <= x_reg_i((n-1) downto 1);
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x_reg_i((n-2) downto 0) <= x_reg_i((n-1) downto 1);
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else -- else remember state
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else -- else remember state
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x_reg_i <= x_reg_i;
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x_reg_i <= x_reg_i;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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with p_sel select -- pipeline select
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with p_sel select -- pipeline select
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x_i <= x_reg_i(offset) when "10", -- use bit at offset for high part of pipeline
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x_i <= x_reg_i(offset) when "10", -- use bit at offset for high part of pipeline
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x_reg_i(0) when others; -- use LS bit for lower part of pipeline
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x_reg_i(0) when others; -- use LS bit for lower part of pipeline
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end Behavioral;
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end Behavioral;
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