| Line 57... |
Line 57... |
end axi_tb;
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end axi_tb;
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|
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architecture arch of axi_tb is
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architecture arch of axi_tb is
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-- constants
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-- constants
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constant CLK_PERIOD : time := 10 ns;
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constant CLK_PERIOD : time := 10 ns;
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constant CORE_CLK_PERIOD : time := 4 ns;
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constant C_S_AXI_DATA_WIDTH : integer := 32;
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constant C_S_AXI_DATA_WIDTH : integer := 32;
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constant C_S_AXI_ADDR_WIDTH : integer := 32;
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constant C_S_AXI_ADDR_WIDTH : integer := 32;
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|
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file output : text open write_mode is "out/axi_output.txt";
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file output : text open write_mode is "out/axi_output.txt";
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|
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| Line 69... |
Line 70... |
------------------------------------------------------------------
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------------------------------------------------------------------
|
constant C_NR_BITS_TOTAL : integer := 1536;
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constant C_NR_BITS_TOTAL : integer := 1536;
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constant C_NR_STAGES_TOTAL : integer := 96;
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constant C_NR_STAGES_TOTAL : integer := 96;
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constant C_NR_STAGES_LOW : integer := 32;
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constant C_NR_STAGES_LOW : integer := 32;
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constant C_SPLIT_PIPELINE : boolean := true;
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constant C_SPLIT_PIPELINE : boolean := true;
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constant C_FIFO_DEPTH : integer := 32; -- set to (maximum exponent width)/16
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constant C_FIFO_AW : integer := 7; -- set to log2( (maximum exponent width)/16 )
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constant C_MEM_STYLE : string := "generic"; -- xil_prim, generic, asym are valid options
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constant C_MEM_STYLE : string := "generic"; -- xil_prim, generic, asym are valid options
|
constant C_FPGA_MAN : string := "xilinx"; -- xilinx, altera are valid options
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constant C_FPGA_MAN : string := "xilinx"; -- xilinx, altera are valid options
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constant C_BASEADDR : std_logic_vector(0 to 31) := x"A0000000";
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constant C_BASEADDR : std_logic_vector(0 to 31) := x"A0000000";
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constant C_HIGHADDR : std_logic_vector(0 to 31) := x"A0007FFF";
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constant C_HIGHADDR : std_logic_vector(0 to 31) := x"A0007FFF";
|
|
|
|
|
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signal core_clk : std_logic := '0';
|
-------------------------
|
-------------------------
|
-- AXI4lite interface
|
-- AXI4lite interface
|
-------------------------
|
-------------------------
|
--- Global signals
|
--- Global signals
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signal S_AXI_ACLK : std_logic;
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signal S_AXI_ACLK : std_logic;
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| Line 119... |
Line 122... |
S_AXI_ACLK <= '1';
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S_AXI_ACLK <= '1';
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wait for CLK_PERIOD/2;
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wait for CLK_PERIOD/2;
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end loop;
|
end loop;
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end process;
|
end process;
|
|
|
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core_clk_process : process
|
|
begin
|
|
while (true) loop
|
|
core_clk <= '0';
|
|
wait for CORE_CLK_PERIOD/2;
|
|
core_clk <= '1';
|
|
wait for CORE_CLK_PERIOD/2;
|
|
end loop;
|
|
end process;
|
|
|
|
|
stim_proc : process
|
stim_proc : process
|
|
|
variable Lw : line;
|
variable Lw : line;
|
|
|
| Line 264... |
Line 277... |
generic map(
|
generic map(
|
C_NR_BITS_TOTAL => C_NR_BITS_TOTAL,
|
C_NR_BITS_TOTAL => C_NR_BITS_TOTAL,
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C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
|
C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
|
C_NR_STAGES_LOW => C_NR_STAGES_LOW,
|
C_NR_STAGES_LOW => C_NR_STAGES_LOW,
|
C_SPLIT_PIPELINE => C_SPLIT_PIPELINE,
|
C_SPLIT_PIPELINE => C_SPLIT_PIPELINE,
|
C_FIFO_DEPTH => C_FIFO_DEPTH,
|
C_FIFO_AW => C_FIFO_AW,
|
C_MEM_STYLE => C_MEM_STYLE, -- xil_prim, generic, asym are valid options
|
C_MEM_STYLE => C_MEM_STYLE, -- xil_prim, generic, asym are valid options
|
C_FPGA_MAN => C_FPGA_MAN, -- xilinx, altera are valid options
|
C_FPGA_MAN => C_FPGA_MAN, -- xilinx, altera are valid options
|
C_BASEADDR => C_BASEADDR,
|
C_BASEADDR => C_BASEADDR,
|
C_HIGHADDR => C_HIGHADDR
|
C_HIGHADDR => C_HIGHADDR
|
)
|
)
|
port map(
|
port map(
|
--USER ports
|
--USER ports
|
|
core_clk => core_clk,
|
-------------------------
|
-------------------------
|
-- AXI4lite interface
|
-- AXI4lite interface
|
-------------------------
|
-------------------------
|
--- Global signals
|
--- Global signals
|
S_AXI_ACLK => S_AXI_ACLK,
|
S_AXI_ACLK => S_AXI_ACLK,
|
