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[/] [mod_sim_exp/] [trunk/] [bench/] [vhdl/] [axi_tb.vhd] - Diff between revs 84 and 94

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Rev 84 Rev 94
Line 57... Line 57...
end axi_tb;
end axi_tb;
 
 
architecture arch of axi_tb is
architecture arch of axi_tb is
  -- constants
  -- constants
  constant CLK_PERIOD : time := 10 ns;
  constant CLK_PERIOD : time := 10 ns;
 
  constant CORE_CLK_PERIOD : time := 4 ns;
  constant C_S_AXI_DATA_WIDTH : integer := 32;
  constant C_S_AXI_DATA_WIDTH : integer := 32;
  constant C_S_AXI_ADDR_WIDTH : integer := 32;
  constant C_S_AXI_ADDR_WIDTH : integer := 32;
 
 
  file output : text open write_mode is "out/axi_output.txt";
  file output : text open write_mode is "out/axi_output.txt";
 
 
Line 69... Line 70...
  ------------------------------------------------------------------
  ------------------------------------------------------------------
  constant C_NR_BITS_TOTAL   : integer := 1536;
  constant C_NR_BITS_TOTAL   : integer := 1536;
  constant C_NR_STAGES_TOTAL : integer := 96;
  constant C_NR_STAGES_TOTAL : integer := 96;
  constant C_NR_STAGES_LOW   : integer := 32;
  constant C_NR_STAGES_LOW   : integer := 32;
  constant C_SPLIT_PIPELINE  : boolean := true;
  constant C_SPLIT_PIPELINE  : boolean := true;
  constant C_FIFO_DEPTH      : integer := 32; -- set to (maximum exponent width)/16
  constant C_FIFO_AW         : integer := 7; -- set to log2( (maximum exponent width)/16 )
  constant C_MEM_STYLE       : string  := "generic"; -- xil_prim, generic, asym are valid options
  constant C_MEM_STYLE       : string  := "generic"; -- xil_prim, generic, asym are valid options
  constant C_FPGA_MAN        : string  := "xilinx";  -- xilinx, altera are valid options
  constant C_FPGA_MAN        : string  := "xilinx";  -- xilinx, altera are valid options
  constant C_BASEADDR        : std_logic_vector(0 to 31) := x"A0000000";
  constant C_BASEADDR        : std_logic_vector(0 to 31) := x"A0000000";
  constant C_HIGHADDR        : std_logic_vector(0 to 31) := x"A0007FFF";
  constant C_HIGHADDR        : std_logic_vector(0 to 31) := x"A0007FFF";
 
 
 
 
 
  signal core_clk     : std_logic := '0';
  -------------------------
  -------------------------
  -- AXI4lite interface
  -- AXI4lite interface
  -------------------------
  -------------------------
  --- Global signals
  --- Global signals
  signal S_AXI_ACLK    : std_logic;
  signal S_AXI_ACLK    : std_logic;
Line 119... Line 122...
      S_AXI_ACLK <= '1';
      S_AXI_ACLK <= '1';
      wait for CLK_PERIOD/2;
      wait for CLK_PERIOD/2;
    end loop;
    end loop;
  end process;
  end process;
 
 
 
  core_clk_process : process
 
  begin
 
    while (true) loop
 
      core_clk <= '0';
 
      wait for CORE_CLK_PERIOD/2;
 
      core_clk <= '1';
 
      wait for CORE_CLK_PERIOD/2;
 
    end loop;
 
  end process;
 
 
 
 
  stim_proc : process
  stim_proc : process
 
 
    variable Lw : line;
    variable Lw : line;
 
 
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  generic map(
  generic map(
    C_NR_BITS_TOTAL   => C_NR_BITS_TOTAL,
    C_NR_BITS_TOTAL   => C_NR_BITS_TOTAL,
    C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
    C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
    C_NR_STAGES_LOW   => C_NR_STAGES_LOW,
    C_NR_STAGES_LOW   => C_NR_STAGES_LOW,
    C_SPLIT_PIPELINE  => C_SPLIT_PIPELINE,
    C_SPLIT_PIPELINE  => C_SPLIT_PIPELINE,
    C_FIFO_DEPTH      => C_FIFO_DEPTH,
    C_FIFO_AW         => C_FIFO_AW,
    C_MEM_STYLE       => C_MEM_STYLE, -- xil_prim, generic, asym are valid options
    C_MEM_STYLE       => C_MEM_STYLE, -- xil_prim, generic, asym are valid options
    C_FPGA_MAN        => C_FPGA_MAN,   -- xilinx, altera are valid options
    C_FPGA_MAN        => C_FPGA_MAN,   -- xilinx, altera are valid options
    C_BASEADDR        => C_BASEADDR,
    C_BASEADDR        => C_BASEADDR,
    C_HIGHADDR        => C_HIGHADDR
    C_HIGHADDR        => C_HIGHADDR
  )
  )
  port map(
  port map(
    --USER ports
    --USER ports
 
    core_clk => core_clk,
    -------------------------
    -------------------------
    -- AXI4lite interface
    -- AXI4lite interface
    -------------------------
    -------------------------
    --- Global signals
    --- Global signals
    S_AXI_ACLK    => S_AXI_ACLK,
    S_AXI_ACLK    => S_AXI_ACLK,

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