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----------------------------------------------------------------------
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---- mod_sim_exp_core_tb ----
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---- ----
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---- This file is part of the ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- ----
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---- Description ----
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---- testbench for the modular simultaneous exponentiation ----
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---- core. Performs some exponentiations to verify the design ----
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---- Takes input parameters from sim_input.txt en writes ----
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---- result and output to sim_output.txt ----
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---- ----
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---- Dependencies: ----
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---- - multiplier_core ----
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---- ----
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---- Authors: ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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---- - Jonas De Craene, JonasDC@opencores.org ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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library std;
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use std.textio.all;
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library ieee;
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use ieee.std_logic_textio.all;
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library mod_sim_exp;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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entity mod_sim_exp_core_tb is
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end mod_sim_exp_core_tb;
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architecture test of mod_sim_exp_core_tb is
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constant nr_stages : integer := 96;
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constant clk_period : time := 10 ns;
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signal clk : std_logic := '0';
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signal reset : std_logic := '1';
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file input : text open read_mode is "src/sim_input.txt";
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file output : text open write_mode is "out/sim_output.txt";
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------------------------------------------------------------------
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-- Signals for multiplier core memory space
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------------------------------------------------------------------
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signal core_rw_address : std_logic_vector (8 downto 0);
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signal core_data_in : std_logic_vector(31 downto 0);
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signal core_fifo_din : std_logic_vector(31 downto 0);
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signal core_data_out : std_logic_vector(31 downto 0);
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signal core_write_enable : std_logic;
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signal core_fifo_push : std_logic;
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------------------------------------------------------------------
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-- Signals for multiplier core control
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------------------------------------------------------------------
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signal core_start : std_logic;
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signal core_run_auto : std_logic;
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signal core_p_sel : std_logic_vector(1 downto 0);
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signal core_dest_op_single : std_logic_vector(1 downto 0);
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signal core_x_sel_single : std_logic_vector(1 downto 0);
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signal core_y_sel_single : std_logic_vector(1 downto 0);
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signal calc_time : std_logic;
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------------------------------------------------------------------
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-- Signals for multiplier core interrupt
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------------------------------------------------------------------
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signal core_fifo_full : std_logic;
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signal core_fifo_nopush : std_logic;
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signal core_ready : std_logic;
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signal core_mem_collision : std_logic;
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begin
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------------------------------------------
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-- Generate clk
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------------------------------------------
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clk_process : process
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begin
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while (true) loop
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end loop;
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end process;
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------------------------------------------
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-- Stimulus Process
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------------------------------------------
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stim_proc : process
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procedure waitclk(n : natural := 1) is
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begin
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for i in 1 to n loop
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wait until rising_edge(clk);
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end loop;
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end waitclk;
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procedure loadOp(constant op_sel : std_logic_vector(2 downto 0);
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variable op_data : std_logic_vector(2047 downto 0)) is
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begin
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wait until rising_edge(clk);
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core_rw_address <= op_sel & "000000";
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wait until rising_edge(clk);
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core_write_enable <= '1';
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for i in 0 to (1536/32)-1 loop
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assert (core_mem_collision='0')
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report "collision detected while writing operand!!" severity failure;
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case (core_p_sel) is
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when "11" =>
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core_data_in <= op_data(((i+1)*32)-1 downto (i*32));
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when "01" =>
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if (i < 16) then core_data_in <= op_data(((i+1)*32)-1 downto (i*32));
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else core_data_in <= x"00000000"; end if;
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when "10" =>
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if (i >= 16) then core_data_in <= op_data(((i-15)*32)-1 downto ((i-16)*32));
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else core_data_in <= x"00000000"; end if;
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when others =>
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core_data_in <= x"00000000";
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end case;
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wait until rising_edge(clk);
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core_rw_address <= core_rw_address+"000000001";
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end loop;
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core_write_enable <= '0';
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wait until rising_edge(clk);
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end loadOp;
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procedure readOp(constant op_sel : std_logic_vector(2 downto 0);
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variable op_data : out std_logic_vector(2047 downto 0);
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variable op_width : integer) is
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begin
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wait until rising_edge(clk);
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core_dest_op_single <= op_sel(1 downto 0);
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if (core_p_sel = "10") then
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core_rw_address <= op_sel & "010000";
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else
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core_rw_address <= op_sel & "000000";
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end if;
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waitclk(2);
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for i in 0 to (op_width/32)-2 loop
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op_data(((i+1)*32)-1 downto (i*32)) := core_data_out;
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core_rw_address <= core_rw_address+"000000001";
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waitclk(2);
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end loop;
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op_data(op_width-1 downto op_width-32) := core_data_out;
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wait until rising_edge(clk);
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end readOp;
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function ToString(constant Timeval : time) return string is
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variable StrPtr : line;
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begin
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write(StrPtr,Timeval);
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return StrPtr.all;
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end ToString;
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-- variables to read file
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variable L : line;
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variable Lw : line;
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variable base_width : integer;
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variable exponent_width : integer;
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variable g0 : std_logic_vector(2047 downto 0) := (others=>'0');
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variable g1 : std_logic_vector(2047 downto 0) := (others=>'0');
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variable e0 : std_logic_vector(2047 downto 0) := (others=>'0');
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variable e1 : std_logic_vector(2047 downto 0) := (others=>'0');
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variable m : std_logic_vector(2047 downto 0) := (others=>'0');
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variable R2 : std_logic_vector(2047 downto 0) := (others=>'0');
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variable R : std_logic_vector(2047 downto 0) := (others=>'0');
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variable gt0 : std_logic_vector(2047 downto 0) := (others=>'0');
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variable gt1 : std_logic_vector(2047 downto 0) := (others=>'0');
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variable gt01 : std_logic_vector(2047 downto 0) := (others=>'0');
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variable one : std_logic_vector(2047 downto 0) := std_logic_vector(conv_unsigned(1, 2048));
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variable result : std_logic_vector(2047 downto 0) := (others=>'0');
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variable data_read : std_logic_vector(2047 downto 0) := (others=>'0');
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variable good_value : boolean;
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variable param_count : integer := 0;
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-- constants for operand selection
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constant op_modulus : std_logic_vector(2 downto 0) := "100";
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constant op_0 : std_logic_vector(2 downto 0) := "000";
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constant op_1 : std_logic_vector(2 downto 0) := "001";
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constant op_2 : std_logic_vector(2 downto 0) := "010";
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constant op_3 : std_logic_vector(2 downto 0) := "011";
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|
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variable timer : time;
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begin
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-- initialisation
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-- memory
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core_write_enable <= '0';
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core_data_in <= x"00000000";
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core_rw_address <= "000000000";
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-- fifo
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core_fifo_din <= x"00000000";
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core_fifo_push <= '0';
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-- control
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core_start <= '0';
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core_run_auto <= '0';
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core_x_sel_single <= "00";
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core_y_sel_single <= "01";
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core_dest_op_single <= "01";
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core_p_sel <= "11";
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|
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-- Generate active high reset signal
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reset <= '1';
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waitclk(100);
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reset <= '0';
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waitclk(100);
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while not endfile(input) loop
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readline(input, L); -- read next line
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next when L(1)='-'; -- skip comment lines
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-- read input values
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case param_count is
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when 0 => -- base width
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read(L, base_width, good_value);
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assert good_value report "Can not read base width" severity failure;
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assert false report "Simulating exponentiation" severity note;
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write(Lw, string'("----------------------------------------------"));
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writeline(output, Lw);
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write(Lw, string'("-- EXPONENTIATION --"));
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writeline(output, Lw);
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write(Lw, string'("----------------------------------------------"));
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writeline(output, Lw);
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write(Lw, string'("----- Variables used:"));
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writeline(output, Lw);
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write(Lw, string'("base width: "));
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write(Lw, base_width);
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writeline(output, Lw);
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case (base_width) is
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when 1536 => when 1024 => when 512 =>
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when others =>
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write(Lw, string'("=> incompatible base width!!!")); writeline(output, Lw);
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assert false report "incompatible base width!!!" severity failure;
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end case;
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when 1 => -- exponent width
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read(L, exponent_width, good_value);
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assert good_value report "Can not read exponent width" severity failure;
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write(Lw, string'("exponent width: "));
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write(Lw, exponent_width);
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writeline(output, Lw);
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when 2 => -- g0
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hread(L, g0(base_width-1 downto 0), good_value);
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assert good_value report "Can not read g0! (wrong lenght?)" severity failure;
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write(Lw, string'("g0: "));
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hwrite(Lw, g0(base_width-1 downto 0));
|
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writeline(output, Lw);
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when 3 => -- g1
|
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hread(L, g1(base_width-1 downto 0), good_value);
|
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assert good_value report "Can not read g1! (wrong lenght?)" severity failure;
|
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write(Lw, string'("g1: "));
|
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hwrite(Lw, g1(base_width-1 downto 0));
|
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writeline(output, Lw);
|
|
|
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when 4 => -- e0
|
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hread(L, e0(exponent_width-1 downto 0), good_value);
|
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assert good_value report "Can not read e0! (wrong lenght?)" severity failure;
|
|
write(Lw, string'("e0: "));
|
|
hwrite(Lw, e0(exponent_width-1 downto 0));
|
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writeline(output, Lw);
|
|
|
|
when 5 => -- e1
|
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hread(L, e1(exponent_width-1 downto 0), good_value);
|
|
assert good_value report "Can not read e1! (wrong lenght?)" severity failure;
|
|
write(Lw, string'("e1: "));
|
|
hwrite(Lw, e1(exponent_width-1 downto 0));
|
|
writeline(output, Lw);
|
|
|
|
when 6 => -- m
|
|
hread(L, m(base_width-1 downto 0), good_value);
|
|
assert good_value report "Can not read m! (wrong lenght?)" severity failure;
|
|
write(Lw, string'("m: "));
|
|
hwrite(Lw, m(base_width-1 downto 0));
|
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writeline(output, Lw);
|
|
|
|
when 7 => -- R^2
|
|
hread(L, R2(base_width-1 downto 0), good_value);
|
|
assert good_value report "Can not read R2! (wrong lenght?)" severity failure;
|
|
write(Lw, string'("R2: "));
|
|
hwrite(Lw, R2(base_width-1 downto 0));
|
|
writeline(output, Lw);
|
|
|
|
when 8 => -- R
|
|
hread(L, R(base_width-1 downto 0), good_value);
|
|
assert good_value report "Can not read R! (wrong lenght?)" severity failure;
|
|
|
|
when 9 => -- gt0
|
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hread(L, gt0(base_width-1 downto 0), good_value);
|
|
assert good_value report "Can not read gt0! (wrong lenght?)" severity failure;
|
|
|
|
when 10 => -- gt1
|
|
hread(L, gt1(base_width-1 downto 0), good_value);
|
|
assert good_value report "Can not read gt1! (wrong lenght?)" severity failure;
|
|
|
|
when 11 => -- gt01
|
|
hread(L, gt01(base_width-1 downto 0), good_value);
|
|
assert good_value report "Can not read gt01! (wrong lenght?)" severity failure;
|
|
|
|
-- select pipeline for all computations
|
|
----------------------------------------
|
|
writeline(output, Lw);
|
|
write(Lw, string'("----- Selecting pipeline: "));
|
|
writeline(output, Lw);
|
|
case (base_width) is
|
|
when 1536 => core_p_sel <= "11"; write(Lw, string'(" Full pipeline selected"));
|
|
when 1024 => core_p_sel <= "10"; write(Lw, string'(" Upper pipeline selected"));
|
|
when 512 => core_p_sel <= "01"; write(Lw, string'(" Lower pipeline selected"));
|
|
when others =>
|
|
write(Lw, string'(" Invallid bitwidth for design"));
|
|
assert false report "impossible basewidth!" severity failure;
|
|
end case;
|
|
writeline(output, Lw);
|
|
|
|
writeline(output, Lw);
|
|
write(Lw, string'("----- Writing operands:"));
|
|
writeline(output, Lw);
|
|
|
|
-- load the modulus
|
|
--------------------
|
|
loadOp(op_modulus, m); -- visual check needed
|
|
write(Lw, string'(" m written"));
|
|
writeline(output, Lw);
|
|
|
|
-- load g0
|
|
-----------
|
|
loadOp(op_0, g0);
|
|
-- verify
|
|
readOp(op_0, data_read, base_width);
|
|
if (g0(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
|
|
write(Lw, string'(" g0 written in operand_0")); writeline(output, Lw);
|
|
else
|
|
write(Lw, string'(" failed to write g0 to operand_0!")); writeline(output, Lw);
|
|
assert false report "Load g0 to op0 data verify failed!!" severity failure;
|
|
end if;
|
|
|
|
-- load g1
|
|
-----------
|
|
loadOp(op_1, g1);
|
|
-- verify
|
|
readOp(op_1, data_read, base_width);
|
|
if (g1(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
|
|
write(Lw, string'(" g1 written in operand_1")); writeline(output, Lw);
|
|
else
|
|
write(Lw, string'(" failed to write g1 to operand_1!")); writeline(output, Lw);
|
|
assert false report "Load g1 to op1 data verify failed!!" severity failure;
|
|
end if;
|
|
|
|
-- load R2
|
|
-----------
|
|
loadOp(op_2, R2);
|
|
-- verify
|
|
readOp(op_2, data_read, base_width);
|
|
if (R2(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
|
|
write(Lw, string'(" R^2 written in operand_2")); writeline(output, Lw);
|
|
else
|
|
write(Lw, string'(" failed to write R^2 to operand_2!")); writeline(output, Lw);
|
|
assert false report "Load R2 to op2 data verify failed!!" severity failure;
|
|
end if;
|
|
|
|
-- load a=1
|
|
------------
|
|
loadOp(op_3, one);
|
|
-- verify
|
|
readOp(op_3, data_read, base_width);
|
|
if (one(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
|
|
write(Lw, string'(" 1 written in operand_3")); writeline(output, Lw);
|
|
else
|
|
write(Lw, string'(" failed to write 1 to operand_3!")); writeline(output, Lw);
|
|
assert false report "Load 1 to op3 data verify failed!!" severity failure;
|
|
end if;
|
|
|
|
writeline(output, Lw);
|
|
write(Lw, string'("----- Pre-computations: "));
|
|
writeline(output, Lw);
|
|
|
|
-- compute gt0
|
|
---------------
|
|
core_x_sel_single <= "00"; -- g0
|
|
core_y_sel_single <= "10"; -- R^2
|
|
core_dest_op_single <= "00"; -- op_0 = (g0 * R) mod m
|
|
wait until rising_edge(clk);
|
|
timer := NOW;
|
|
core_start <= '1';
|
|
wait until rising_edge(clk);
|
|
core_start <= '0';
|
|
wait until core_ready = '1';
|
|
timer := NOW-timer;
|
|
waitclk(10);
|
|
readOp(op_0, data_read, base_width);
|
|
write(Lw, string'(" Computed gt0: "));
|
|
hwrite(Lw, data_read(base_width-1 downto 0));
|
|
writeline(output, Lw);
|
|
write(Lw, string'(" Read gt0: "));
|
|
hwrite(Lw, gt0(base_width-1 downto 0));
|
|
writeline(output, Lw);
|
|
write(Lw, string'(" => calc time is "));
|
|
write(Lw, string'(ToString(timer)));
|
|
writeline(output, Lw);
|
|
write(Lw, string'(" => expected time is "));
|
|
write(Lw, (nr_stages+(2*(base_width-1)))*clk_period);
|
|
writeline(output, Lw);
|
|
if (gt0(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
|
|
write(Lw, string'(" => gt0 is correct!")); writeline(output, Lw);
|
|
else
|
|
write(Lw, string'(" => Error: gt0 is incorrect!!!")); writeline(output, Lw);
|
|
assert false report "gt0 is incorrect!!!" severity failure;
|
|
end if;
|
|
|
|
-- compute gt1
|
|
---------------
|
|
core_x_sel_single <= "01"; -- g1
|
|
core_y_sel_single <= "10"; -- R^2
|
|
core_dest_op_single <= "01"; -- op_1 = (g1 * R) mod m
|
|
wait until rising_edge(clk);
|
|
timer := NOW;
|
|
core_start <= '1';
|
|
wait until rising_edge(clk);
|
|
core_start <= '0';
|
|
wait until core_ready = '1';
|
|
timer := NOW-timer;
|
|
waitclk(10);
|
|
readOp(op_1, data_read, base_width);
|
|
write(Lw, string'(" Computed gt1: "));
|
|
hwrite(Lw, data_read(base_width-1 downto 0));
|
|
writeline(output, Lw);
|
|
write(Lw, string'(" Read gt1: "));
|
|
hwrite(Lw, gt1(base_width-1 downto 0));
|
|
writeline(output, Lw);
|
|
write(Lw, string'(" => calc time is "));
|
|
write(Lw, string'(ToString(timer)));
|
|
writeline(output, Lw);
|
|
write(Lw, string'(" => expected time is "));
|
|
write(Lw, (nr_stages+(2*(base_width-1)))*clk_period);
|
|
writeline(output, Lw);
|
|
if (gt1(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
|
|
write(Lw, string'(" => gt1 is correct!")); writeline(output, Lw);
|
|
else
|
|
write(Lw, string'(" => Error: gt1 is incorrect!!!")); writeline(output, Lw);
|
|
assert false report "gt1 is incorrect!!!" severity failure;
|
|
end if;
|
|
|
|
-- compute a
|
|
-------------
|
|
core_x_sel_single <= "10"; -- R^2
|
|
core_y_sel_single <= "11"; -- 1
|
|
core_dest_op_single <= "11"; -- op_3 = (R) mod m
|
|
wait until rising_edge(clk);
|
|
core_start <= '1';
|
|
timer := NOW;
|
|
wait until rising_edge(clk);
|
|
core_start <= '0';
|
|
wait until core_ready = '1';
|
|
timer := NOW-timer;
|
|
waitclk(10);
|
|
readOp(op_3, data_read, base_width);
|
|
write(Lw, string'(" Computed a=(R)mod m: "));
|
|
hwrite(Lw, data_read(base_width-1 downto 0));
|
|
writeline(output, Lw);
|
|
write(Lw, string'(" Read (R)mod m: "));
|
|
hwrite(Lw, R(base_width-1 downto 0));
|
|
writeline(output, Lw);
|
|
write(Lw, string'(" => calc time is "));
|
|
write(Lw, string'(ToString(timer)));
|
|
writeline(output, Lw);
|
|
write(Lw, string'(" => expected time is "));
|
|
write(Lw, (nr_stages+(2*(base_width-1)))*clk_period);
|
|
writeline(output, Lw);
|
|
if (R(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
|
|
write(Lw, string'(" => (R)mod m is correct!")); writeline(output, Lw);
|
|
else
|
|
write(Lw, string'(" => Error: (R)mod m is incorrect!!!")); writeline(output, Lw);
|
|
assert false report "(R)mod m is incorrect!!!" severity failure;
|
|
end if;
|
|
|
|
-- compute gt01
|
|
---------------
|
|
core_x_sel_single <= "00"; -- gt0
|
|
core_y_sel_single <= "01"; -- gt1
|
|
core_dest_op_single <= "10"; -- op_2 = (gt0 * gt1) mod m
|
|
wait until rising_edge(clk);
|
|
core_start <= '1';
|
|
timer := NOW;
|
|
wait until rising_edge(clk);
|
|
core_start <= '0';
|
|
wait until core_ready = '1';
|
|
timer := NOW-timer;
|
|
waitclk(10);
|
|
readOp(op_2, data_read, base_width);
|
|
write(Lw, string'(" Computed gt01: "));
|
|
hwrite(Lw, data_read(base_width-1 downto 0));
|
|
writeline(output, Lw);
|
|
write(Lw, string'(" Read gt01: "));
|
|
hwrite(Lw, gt01(base_width-1 downto 0));
|
|
writeline(output, Lw);
|
|
write(Lw, string'(" => calc time is "));
|
|
write(Lw, string'(ToString(timer)));
|
|
writeline(output, Lw);
|
|
write(Lw, string'(" => expected time is "));
|
|
write(Lw, (nr_stages+(2*(base_width-1)))*clk_period);
|
|
writeline(output, Lw);
|
|
if (gt01(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
|
|
write(Lw, string'(" => gt01 is correct!")); writeline(output, Lw);
|
|
else
|
|
write(Lw, string'(" => Error: gt01 is incorrect!!!")); writeline(output, Lw);
|
|
assert false report "gt01 is incorrect!!!" severity failure;
|
|
end if;
|
|
|
|
-- load exponent fifo
|
|
----------------------
|
|
writeline(output, Lw);
|
|
write(Lw, string'("----- Loading exponent fifo: "));
|
|
writeline(output, Lw);
|
|
for i in (exponent_width/16)-1 downto 0 loop
|
|
core_fifo_din <= e1((i*16)+15 downto (i*16)) & e0((i*16)+15 downto (i*16));
|
|
wait until rising_edge(clk);
|
|
core_fifo_push <= '1';
|
|
wait until rising_edge(clk);
|
|
assert (core_fifo_full='0' and core_fifo_nopush='0')
|
|
report "Fifo error, full or nopush" severity failure;
|
|
core_fifo_push <= '0';
|
|
wait until rising_edge(clk);
|
|
end loop;
|
|
waitclk(10);
|
|
write(Lw, string'(" => Done"));
|
|
writeline(output, Lw);
|
|
|
|
-- start exponentiation
|
|
------------------------
|
|
writeline(output, Lw);
|
|
write(Lw, string'("----- Starting exponentiation: "));
|
|
writeline(output, Lw);
|
|
core_run_auto <= '1';
|
|
wait until rising_edge(clk);
|
|
timer := NOW;
|
|
core_start <= '1';
|
|
wait until rising_edge(clk);
|
|
core_start <= '0';
|
|
wait until core_ready='1';
|
|
timer := NOW-timer;
|
|
waitclk(10);
|
|
write(Lw, string'(" => calc time is "));
|
|
write(Lw, string'(ToString(timer)));
|
|
writeline(output, Lw);
|
|
write(Lw, string'(" => expected time is "));
|
|
write(Lw, ((nr_stages+(2*(base_width-1)))*clk_period*7*exponent_width)/4);
|
|
writeline(output, Lw);
|
|
write(Lw, string'(" => Done"));
|
|
core_run_auto <= '0';
|
|
writeline(output, Lw);
|
|
|
|
-- post-computations
|
|
---------------------
|
|
writeline(output, Lw);
|
|
write(Lw, string'("----- Post-computations: "));
|
|
writeline(output, Lw);
|
|
-- load in 1 to operand 2
|
|
loadOp(op_2, one);
|
|
-- verify
|
|
readOp(op_2, data_read, base_width);
|
|
if (one(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
|
|
write(Lw, string'(" 1 written in operand_2")); writeline(output, Lw);
|
|
else
|
|
write(Lw, string'(" failed to write 1 to operand_2!")); writeline(output, Lw);
|
|
assert false report "Load 1 to op2 data verify failed!!" severity failure;
|
|
end if;
|
|
-- compute result
|
|
core_x_sel_single <= "11"; -- a
|
|
core_y_sel_single <= "10"; -- 1
|
|
core_dest_op_single <= "11"; -- op_3 = (a) mod m
|
|
wait until rising_edge(clk);
|
|
timer := NOW;
|
|
core_start <= '1';
|
|
wait until rising_edge(clk);
|
|
core_start <= '0';
|
|
wait until core_ready = '1';
|
|
timer := NOW-timer;
|
|
waitclk(10);
|
|
readOp(op_3, data_read, base_width);
|
|
write(Lw, string'(" Computed result: "));
|
|
hwrite(Lw, data_read(base_width-1 downto 0));
|
|
writeline(output, Lw);
|
|
write(Lw, string'(" => calc time is "));
|
|
write(Lw, string'(ToString(timer)));
|
|
writeline(output, Lw);
|
|
write(Lw, string'(" => expected time is "));
|
|
write(Lw, (nr_stages+(2*(base_width-1)))*clk_period);
|
|
writeline(output, Lw);
|
|
|
|
when 12 => -- check with result
|
|
hread(L, result(base_width-1 downto 0), good_value);
|
|
assert good_value report "Can not read result! (wrong lenght?)" severity failure;
|
|
writeline(output, Lw);
|
|
write(Lw, string'("----- verifying result: "));
|
|
writeline(output, Lw);
|
|
write(Lw, string'(" Read result: "));
|
|
hwrite(Lw, result(base_width-1 downto 0));
|
|
writeline(output, Lw);
|
|
write(Lw, string'(" Computed result: "));
|
|
hwrite(Lw, data_read(base_width-1 downto 0));
|
|
writeline(output, Lw);
|
|
if (result(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
|
|
write(Lw, string'(" => Result is correct!")); writeline(output, Lw);
|
|
else
|
|
write(Lw, string'(" Error: result is incorrect!!!")); writeline(output, Lw);
|
|
assert false report "result is incorrect!!!" severity failure;
|
|
end if;
|
|
writeline(output, Lw);
|
|
|
|
when others =>
|
|
assert false report "undefined state!" severity failure;
|
|
end case;
|
|
|
|
if (param_count = 12) then
|
|
param_count := 0;
|
|
else
|
|
param_count := param_count+1;
|
|
end if;
|
|
end loop;
|
|
|
|
wait for 1 us;
|
|
assert false report "End of simulation" severity failure;
|
|
|
|
end process;
|
|
|
|
------------------------------------------
|
|
-- Multiplier core instance
|
|
------------------------------------------
|
|
the_multiplier : mod_sim_exp.mod_sim_exp_pkg.mod_sim_exp_core
|
|
port map(
|
|
clk => clk,
|
|
reset => reset,
|
|
-- operand memory interface (plb shared memory)
|
|
write_enable => core_write_enable,
|
|
data_in => core_data_in,
|
|
rw_address => core_rw_address,
|
|
data_out => core_data_out,
|
|
collision => core_mem_collision,
|
|
-- op_sel fifo interface
|
|
fifo_din => core_fifo_din,
|
|
fifo_push => core_fifo_push,
|
|
fifo_full => core_fifo_full,
|
|
fifo_nopush => core_fifo_nopush,
|
|
-- ctrl signals
|
|
start => core_start,
|
|
run_auto => core_run_auto,
|
|
ready => core_ready,
|
|
x_sel_single => core_x_sel_single,
|
|
y_sel_single => core_y_sel_single,
|
|
dest_op_single => core_dest_op_single,
|
|
p_sel => core_p_sel,
|
|
calc_time => calc_time
|
|
);
|
|
|
|
end test;
|
|
|
No newline at end of file
|
No newline at end of file
|
