| Line 61... |
Line 61... |
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entity mod_sim_exp_core_tb is
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entity mod_sim_exp_core_tb is
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end mod_sim_exp_core_tb;
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end mod_sim_exp_core_tb;
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architecture test of mod_sim_exp_core_tb is
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architecture test of mod_sim_exp_core_tb is
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constant clk_period : time := 10 ns;
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constant CLK_PERIOD : time := 10 ns;
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signal clk : std_logic := '0';
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signal clk : std_logic := '0';
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signal reset : std_logic := '1';
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signal reset : std_logic := '1';
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file input : text open read_mode is "src/sim_input.txt";
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file input : text open read_mode is "src/sim_input.txt";
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file output : text open write_mode is "out/sim_output.txt";
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file output : text open write_mode is "out/sim_output.txt";
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------------------------------------------------------------------
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------------------------------------------------------------------
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-- Core parameters
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------------------------------------------------------------------
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constant C_NR_BITS_TOTAL : integer := 1536;
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constant C_NR_STAGES_TOTAL : integer := 96;
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constant C_NR_STAGES_LOW : integer := 32;
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constant C_SPLIT_PIPELINE : boolean := true;
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-- extra calculated constants
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constant NR_BITS_LOW : integer := (C_NR_BITS_TOTAL/C_NR_STAGES_TOTAL)*C_NR_STAGES_LOW;
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constant NR_BITS_HIGH : integer := C_NR_BITS_TOTAL-NR_BITS_LOW;
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------------------------------------------------------------------
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-- Signals for multiplier core memory space
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-- Signals for multiplier core memory space
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------------------------------------------------------------------
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------------------------------------------------------------------
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signal core_rw_address : std_logic_vector (8 downto 0);
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signal core_rw_address : std_logic_vector (8 downto 0);
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signal core_data_in : std_logic_vector(31 downto 0);
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signal core_data_in : std_logic_vector(31 downto 0);
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signal core_fifo_din : std_logic_vector(31 downto 0);
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signal core_fifo_din : std_logic_vector(31 downto 0);
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| Line 103... |
Line 115... |
------------------------------------------
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------------------------------------------
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clk_process : process
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clk_process : process
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begin
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begin
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while (true) loop
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while (true) loop
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clk <= '0';
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clk <= '0';
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wait for clk_period/2;
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wait for CLK_PERIOD/2;
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clk <= '1';
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clk <= '1';
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wait for clk_period/2;
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wait for CLK_PERIOD/2;
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end loop;
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end loop;
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end process;
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end process;
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------------------------------------------
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------------------------------------------
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-- Stimulus Process
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-- Stimulus Process
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| Line 252... |
Line 264... |
writeline(output, Lw);
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writeline(output, Lw);
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write(Lw, string'("base width: "));
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write(Lw, string'("base width: "));
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write(Lw, base_width);
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write(Lw, base_width);
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writeline(output, Lw);
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writeline(output, Lw);
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case (base_width) is
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case (base_width) is
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when nr_bits_total => when nr_bits_high => when nr_bits_low =>
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when C_NR_BITS_TOTAL => when NR_BITS_HIGH => when NR_BITS_LOW =>
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when others =>
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when others =>
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write(Lw, string'("=> incompatible base width!!!")); writeline(output, Lw);
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write(Lw, string'("=> incompatible base width!!!")); writeline(output, Lw);
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assert false report "incompatible base width!!!" severity failure;
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assert false report "incompatible base width!!!" severity failure;
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end case;
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end case;
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| Line 329... |
Line 341... |
----------------------------------------
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----------------------------------------
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writeline(output, Lw);
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writeline(output, Lw);
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write(Lw, string'("----- Selecting pipeline: "));
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write(Lw, string'("----- Selecting pipeline: "));
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writeline(output, Lw);
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writeline(output, Lw);
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case (base_width) is
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case (base_width) is
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when nr_bits_total => core_p_sel <= "11"; write(Lw, string'(" Full pipeline selected"));
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when C_NR_BITS_TOTAL => core_p_sel <= "11"; write(Lw, string'(" Full pipeline selected"));
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when nr_bits_high => core_p_sel <= "10"; write(Lw, string'(" Upper pipeline selected"));
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when NR_BITS_HIGH => core_p_sel <= "10"; write(Lw, string'(" Upper pipeline selected"));
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when nr_bits_low => core_p_sel <= "01"; write(Lw, string'(" Lower pipeline selected"));
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when NR_BITS_LOW => core_p_sel <= "01"; write(Lw, string'(" Lower pipeline selected"));
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when others =>
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when others =>
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write(Lw, string'(" Invallid bitwidth for design"));
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write(Lw, string'(" Invallid bitwidth for design"));
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assert false report "impossible basewidth!" severity failure;
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assert false report "impossible basewidth!" severity failure;
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end case;
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end case;
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writeline(output, Lw);
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writeline(output, Lw);
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| Line 424... |
Line 436... |
writeline(output, Lw);
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writeline(output, Lw);
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write(Lw, string'(" => calc time is "));
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write(Lw, string'(" => calc time is "));
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write(Lw, string'(ToString(timer)));
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write(Lw, string'(ToString(timer)));
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writeline(output, Lw);
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writeline(output, Lw);
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write(Lw, string'(" => expected time is "));
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write(Lw, string'(" => expected time is "));
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write(Lw, (nr_stages_total+(2*(base_width-1)))*clk_period);
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write(Lw, (C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD);
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writeline(output, Lw);
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writeline(output, Lw);
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if (gt0(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
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if (gt0(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
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write(Lw, string'(" => gt0 is correct!")); writeline(output, Lw);
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write(Lw, string'(" => gt0 is correct!")); writeline(output, Lw);
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else
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else
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write(Lw, string'(" => Error: gt0 is incorrect!!!")); writeline(output, Lw);
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write(Lw, string'(" => Error: gt0 is incorrect!!!")); writeline(output, Lw);
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| Line 457... |
Line 469... |
writeline(output, Lw);
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writeline(output, Lw);
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write(Lw, string'(" => calc time is "));
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write(Lw, string'(" => calc time is "));
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write(Lw, string'(ToString(timer)));
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write(Lw, string'(ToString(timer)));
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writeline(output, Lw);
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writeline(output, Lw);
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write(Lw, string'(" => expected time is "));
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write(Lw, string'(" => expected time is "));
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write(Lw, (nr_stages_total+(2*(base_width-1)))*clk_period);
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write(Lw, (C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD);
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writeline(output, Lw);
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writeline(output, Lw);
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if (gt1(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
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if (gt1(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
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write(Lw, string'(" => gt1 is correct!")); writeline(output, Lw);
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write(Lw, string'(" => gt1 is correct!")); writeline(output, Lw);
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else
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else
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write(Lw, string'(" => Error: gt1 is incorrect!!!")); writeline(output, Lw);
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write(Lw, string'(" => Error: gt1 is incorrect!!!")); writeline(output, Lw);
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| Line 490... |
Line 502... |
writeline(output, Lw);
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writeline(output, Lw);
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write(Lw, string'(" => calc time is "));
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write(Lw, string'(" => calc time is "));
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write(Lw, string'(ToString(timer)));
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write(Lw, string'(ToString(timer)));
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writeline(output, Lw);
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writeline(output, Lw);
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write(Lw, string'(" => expected time is "));
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write(Lw, string'(" => expected time is "));
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write(Lw, (nr_stages_total+(2*(base_width-1)))*clk_period);
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write(Lw, (C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD);
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writeline(output, Lw);
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writeline(output, Lw);
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if (R(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
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if (R(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
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write(Lw, string'(" => (R)mod m is correct!")); writeline(output, Lw);
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write(Lw, string'(" => (R)mod m is correct!")); writeline(output, Lw);
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else
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else
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write(Lw, string'(" => Error: (R)mod m is incorrect!!!")); writeline(output, Lw);
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write(Lw, string'(" => Error: (R)mod m is incorrect!!!")); writeline(output, Lw);
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| Line 523... |
Line 535... |
writeline(output, Lw);
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writeline(output, Lw);
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write(Lw, string'(" => calc time is "));
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write(Lw, string'(" => calc time is "));
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write(Lw, string'(ToString(timer)));
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write(Lw, string'(ToString(timer)));
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writeline(output, Lw);
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writeline(output, Lw);
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write(Lw, string'(" => expected time is "));
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write(Lw, string'(" => expected time is "));
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write(Lw, (nr_stages_total+(2*(base_width-1)))*clk_period);
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write(Lw, (C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD);
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writeline(output, Lw);
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writeline(output, Lw);
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if (gt01(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
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if (gt01(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
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write(Lw, string'(" => gt01 is correct!")); writeline(output, Lw);
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write(Lw, string'(" => gt01 is correct!")); writeline(output, Lw);
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else
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else
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write(Lw, string'(" => Error: gt01 is incorrect!!!")); writeline(output, Lw);
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write(Lw, string'(" => Error: gt01 is incorrect!!!")); writeline(output, Lw);
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| Line 569... |
Line 581... |
waitclk(10);
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waitclk(10);
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write(Lw, string'(" => calc time is "));
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write(Lw, string'(" => calc time is "));
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write(Lw, string'(ToString(timer)));
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write(Lw, string'(ToString(timer)));
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writeline(output, Lw);
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writeline(output, Lw);
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write(Lw, string'(" => expected time is "));
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write(Lw, string'(" => expected time is "));
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write(Lw, ((nr_stages_total+(2*(base_width-1)))*clk_period*7*exponent_width)/4);
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write(Lw, ((C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD*7*exponent_width)/4);
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writeline(output, Lw);
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writeline(output, Lw);
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write(Lw, string'(" => Done"));
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write(Lw, string'(" => Done"));
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core_run_auto <= '0';
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core_run_auto <= '0';
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writeline(output, Lw);
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writeline(output, Lw);
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|
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| Line 610... |
Line 622... |
writeline(output, Lw);
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writeline(output, Lw);
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write(Lw, string'(" => calc time is "));
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write(Lw, string'(" => calc time is "));
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write(Lw, string'(ToString(timer)));
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write(Lw, string'(ToString(timer)));
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writeline(output, Lw);
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writeline(output, Lw);
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write(Lw, string'(" => expected time is "));
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write(Lw, string'(" => expected time is "));
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write(Lw, (nr_stages_total+(2*(base_width-1)))*clk_period);
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write(Lw, (C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD);
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writeline(output, Lw);
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writeline(output, Lw);
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|
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when 12 => -- check with result
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when 12 => -- check with result
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hread(L, result(base_width-1 downto 0), good_value);
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hread(L, result(base_width-1 downto 0), good_value);
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assert good_value report "Can not read result! (wrong lenght?)" severity failure;
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assert good_value report "Can not read result! (wrong lenght?)" severity failure;
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| Line 653... |
Line 665... |
|
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------------------------------------------
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------------------------------------------
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-- Multiplier core instance
|
-- Multiplier core instance
|
------------------------------------------
|
------------------------------------------
|
the_multiplier : mod_sim_exp.mod_sim_exp_pkg.mod_sim_exp_core
|
the_multiplier : mod_sim_exp.mod_sim_exp_pkg.mod_sim_exp_core
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|
generic map(
|
|
C_NR_BITS_TOTAL => C_NR_BITS_TOTAL,
|
|
C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
|
|
C_NR_STAGES_LOW => C_NR_STAGES_LOW,
|
|
C_SPLIT_PIPELINE => C_SPLIT_PIPELINE
|
|
)
|
port map(
|
port map(
|
clk => clk,
|
clk => clk,
|
reset => reset,
|
reset => reset,
|
-- operand memory interface (plb shared memory)
|
-- operand memory interface (plb shared memory)
|
write_enable => core_write_enable,
|
write_enable => core_write_enable,
|
