Subversion Repositories mod_sim_exp

  signal core_fifo_push    : std_logic;

  signal core_fifo_push    : std_logic;

  ------------------------------------------------------------------

  ------------------------------------------------------------------

  -- Signals for multiplier core control

  -- Signals for multiplier core control

  ------------------------------------------------------------------

  ------------------------------------------------------------------

  signal core_start          : std_logic;

  signal core_start          : std_logic;

  signal core_p_sel          : std_logic_vector(1 downto 0);

  signal core_p_sel          : std_logic_vector(1 downto 0);

  signal core_dest_op_single : std_logic_vector(1 downto 0);

  signal core_dest_op_single : std_logic_vector(1 downto 0);

  signal core_x_sel_single   : std_logic_vector(1 downto 0);

  signal core_x_sel_single   : std_logic_vector(1 downto 0);

  signal core_y_sel_single   : std_logic_vector(1 downto 0);

  signal core_y_sel_single   : std_logic_vector(1 downto 0);

  signal calc_time           : std_logic;

  signal calc_time           : std_logic;

  -- fifo

  -- fifo

  core_fifo_din <= x"00000000";

  core_fifo_din <= x"00000000";

  core_fifo_push <= '0';

  core_fifo_push <= '0';

  -- control

  -- control

  core_start <= '0';

  core_start <= '0';

  core_x_sel_single <= "00";

  core_x_sel_single <= "00";

  core_y_sel_single <= "01";

  core_y_sel_single <= "01";

  core_dest_op_single <= "01";

  core_dest_op_single <= "01";

  core_p_sel <= "11";

  core_p_sel <= "11";

        -- start exponentiation

        -- start exponentiation

        ------------------------

        ------------------------

        writeline(output, Lw);

        writeline(output, Lw);

        write(Lw, string'("----- Starting exponentiation: "));

        write(Lw, string'("----- Starting exponentiation: "));

        writeline(output, Lw);

        writeline(output, Lw);

        wait until rising_edge(clk);

        wait until rising_edge(clk);

        timer := NOW;

        timer := NOW;

        core_start <= '1';

        core_start <= '1';

        wait until rising_edge(clk);

        wait until rising_edge(clk);

        core_start <= '0';

        core_start <= '0';

        writeline(output, Lw);

        writeline(output, Lw);

        write(Lw, string'("  => expected time is "));

        write(Lw, string'("  => expected time is "));

        write(Lw, ((C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD*7*exponent_width)/4);

        write(Lw, ((C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD*7*exponent_width)/4);

        writeline(output, Lw);

        writeline(output, Lw);

        write(Lw, string'("  => Done"));

        write(Lw, string'("  => Done"));

        writeline(output, Lw);

        writeline(output, Lw);

        -- post-computations

        -- post-computations

        ---------------------

        ---------------------

        writeline(output, Lw);

        writeline(output, Lw);

  fifo_push   => core_fifo_push,

  fifo_push   => core_fifo_push,

  fifo_full   => core_fifo_full,

  fifo_full   => core_fifo_full,

  fifo_nopush => core_fifo_nopush,

  fifo_nopush => core_fifo_nopush,

-- ctrl signals

-- ctrl signals

  start          => core_start,

  start          => core_start,

  ready          => core_ready,

  ready          => core_ready,

  x_sel_single   => core_x_sel_single,

  x_sel_single   => core_x_sel_single,

  y_sel_single   => core_y_sel_single,

  y_sel_single   => core_y_sel_single,

  dest_op_single => core_dest_op_single,

  dest_op_single => core_dest_op_single,

  p_sel          => core_p_sel,

  p_sel          => core_p_sel,