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Line 74... |
------------------------------------------------------------------
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------------------------------------------------------------------
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constant C_NR_BITS_TOTAL : integer := 1536;
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constant C_NR_BITS_TOTAL : integer := 1536;
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constant C_NR_STAGES_TOTAL : integer := 96;
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constant C_NR_STAGES_TOTAL : integer := 96;
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constant C_NR_STAGES_LOW : integer := 32;
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constant C_NR_STAGES_LOW : integer := 32;
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constant C_SPLIT_PIPELINE : boolean := true;
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constant C_SPLIT_PIPELINE : boolean := true;
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constant C_NR_OP : integer := 4; -- leave on 4 for simulation
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constant C_NR_M : integer := 2; -- leave on 2 for simulation
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constant C_FIFO_DEPTH : integer := 32; -- set to (maximum exponent width)/16
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constant C_FIFO_DEPTH : integer := 32; -- set to (maximum exponent width)/16
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constant C_MEM_STYLE : string := "generic"; -- xil_prim, generic, asym are valid options
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constant C_MEM_STYLE : string := "generic"; -- xil_prim, generic, asym are valid options
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constant C_DEVICE : string := "xilinx"; -- xilinx, altera are valid options
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constant C_DEVICE : string := "xilinx"; -- xilinx, altera are valid options
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-- extra calculated constants
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-- extra calculated constants
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Line 675... |
generic map(
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generic map(
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C_NR_BITS_TOTAL => C_NR_BITS_TOTAL,
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C_NR_BITS_TOTAL => C_NR_BITS_TOTAL,
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C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
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C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
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C_NR_STAGES_LOW => C_NR_STAGES_LOW,
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C_NR_STAGES_LOW => C_NR_STAGES_LOW,
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C_SPLIT_PIPELINE => C_SPLIT_PIPELINE,
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C_SPLIT_PIPELINE => C_SPLIT_PIPELINE,
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C_NR_OP => C_NR_OP,
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C_NR_M => C_NR_M,
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C_FIFO_DEPTH => C_FIFO_DEPTH,
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C_FIFO_DEPTH => C_FIFO_DEPTH,
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C_MEM_STYLE => C_MEM_STYLE, -- xil_prim, generic, asym are valid options
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C_MEM_STYLE => C_MEM_STYLE, -- xil_prim, generic, asym are valid options
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C_DEVICE => C_DEVICE -- xilinx, altera are valid options
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C_DEVICE => C_DEVICE -- xilinx, altera are valid options
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)
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)
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port map(
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port map(
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