Line 63... |
Line 63... |
end mod_sim_exp_core_tb;
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end mod_sim_exp_core_tb;
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|
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architecture test of mod_sim_exp_core_tb is
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architecture test of mod_sim_exp_core_tb is
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constant CLK_PERIOD : time := 10 ns;
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constant CLK_PERIOD : time := 10 ns;
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signal clk : std_logic := '0';
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signal clk : std_logic := '0';
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constant CORE_CLK_PERIOD : time := 4 ns;
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signal core_clk : std_logic := '0';
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signal reset : std_logic := '1';
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signal reset : std_logic := '1';
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file input : text open read_mode is "src/sim_input.txt";
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file input : text open read_mode is "src/sim_input.txt";
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file output : text open write_mode is "out/sim_output.txt";
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file output : text open write_mode is "out/sim_output.txt";
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|
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------------------------------------------------------------------
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------------------------------------------------------------------
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Line 74... |
Line 76... |
------------------------------------------------------------------
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------------------------------------------------------------------
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constant C_NR_BITS_TOTAL : integer := 1536;
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constant C_NR_BITS_TOTAL : integer := 1536;
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constant C_NR_STAGES_TOTAL : integer := 96;
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constant C_NR_STAGES_TOTAL : integer := 96;
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constant C_NR_STAGES_LOW : integer := 32;
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constant C_NR_STAGES_LOW : integer := 32;
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constant C_SPLIT_PIPELINE : boolean := true;
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constant C_SPLIT_PIPELINE : boolean := true;
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constant C_FIFO_DEPTH : integer := 32; -- set to (maximum exponent width)/16
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constant C_FIFO_AW : integer := 7; -- set to log2( (maximum exponent width)/16 )
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constant C_MEM_STYLE : string := "asym"; -- xil_prim, generic, asym are valid options
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constant C_MEM_STYLE : string := "asym"; -- xil_prim, generic, asym are valid options
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constant C_FPGA_MAN : string := "xilinx"; -- xilinx, altera are valid options
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constant C_FPGA_MAN : string := "xilinx"; -- xilinx, altera are valid options
|
|
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-- extra calculated constants
|
-- extra calculated constants
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constant NR_BITS_LOW : integer := (C_NR_BITS_TOTAL/C_NR_STAGES_TOTAL)*C_NR_STAGES_LOW;
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constant NR_BITS_LOW : integer := (C_NR_BITS_TOTAL/C_NR_STAGES_TOTAL)*C_NR_STAGES_LOW;
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Line 124... |
Line 126... |
clk <= '1';
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clk <= '1';
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wait for CLK_PERIOD/2;
|
wait for CLK_PERIOD/2;
|
end loop;
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end loop;
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end process;
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end process;
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|
|
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core_clk_process : process
|
|
begin
|
|
while (true) loop
|
|
core_clk <= '0';
|
|
wait for CORE_CLK_PERIOD/2;
|
|
core_clk <= '1';
|
|
wait for CORE_CLK_PERIOD/2;
|
|
end loop;
|
|
end process;
|
|
|
------------------------------------------
|
------------------------------------------
|
-- Stimulus Process
|
-- Stimulus Process
|
------------------------------------------
|
------------------------------------------
|
stim_proc : process
|
stim_proc : process
|
procedure waitclk(n : natural := 1) is
|
procedure waitclk(n : natural := 1) is
|
Line 675... |
Line 687... |
generic map(
|
generic map(
|
C_NR_BITS_TOTAL => C_NR_BITS_TOTAL,
|
C_NR_BITS_TOTAL => C_NR_BITS_TOTAL,
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C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
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C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
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C_NR_STAGES_LOW => C_NR_STAGES_LOW,
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C_NR_STAGES_LOW => C_NR_STAGES_LOW,
|
C_SPLIT_PIPELINE => C_SPLIT_PIPELINE,
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C_SPLIT_PIPELINE => C_SPLIT_PIPELINE,
|
C_FIFO_DEPTH => C_FIFO_DEPTH,
|
C_FIFO_AW => C_FIFO_AW,
|
C_MEM_STYLE => C_MEM_STYLE, -- xil_prim, generic, asym are valid options
|
C_MEM_STYLE => C_MEM_STYLE, -- xil_prim, generic, asym are valid options
|
C_FPGA_MAN => C_FPGA_MAN -- xilinx, altera are valid options
|
C_FPGA_MAN => C_FPGA_MAN -- xilinx, altera are valid options
|
)
|
)
|
port map(
|
port map(
|
clk => clk,
|
bus_clk => clk,
|
|
core_clk => core_clk,
|
reset => reset,
|
reset => reset,
|
-- operand memory interface (plb shared memory)
|
-- operand memory interface (plb shared memory)
|
write_enable => core_write_enable,
|
write_enable => core_write_enable,
|
data_in => core_data_in,
|
data_in => core_data_in,
|
rw_address => core_rw_address,
|
rw_address => core_rw_address,
|