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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [adder_block.vhd] - Diff between revs 9 and 12

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Rev 9 Rev 12
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----  This file is part of the                                    ----
----  This file is part of the                                    ----
----    Modular Simultaneous Exponentiation Core project          ---- 
----    Modular Simultaneous Exponentiation Core project          ---- 
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
----                                                              ---- 
----                                                              ---- 
----  Description                                                 ---- 
----  Description                                                 ---- 
----    Adder block with a flipflop for the carry out             ----
----    Adder block with a flipflop for the carry out so result   ----
 
----    is available after 1 clock cycle                          ----
----    for use in the montgommery multiplier pre and post        ----
----    for use in the montgommery multiplier pre and post        ----
----    computation adders                                        ----
----    computation adders                                        ----
----                                                              ----
----                                                              ----
----  Dependencies:                                               ----
----  Dependencies:                                               ----
----    - cell_1b_adder                                           ----
----    - cell_1b_adder                                           ----
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library mod_sim_exp;
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
 
-- (width)-bit full adder block using cell_1b_adders
-- (width)-bit full adder block using cell_1b_adders
-- with buffered carry out
-- with buffered carry out -> result after 1 clock cycle
entity adder_block is
entity adder_block is
  generic (
  generic (
    width : integer := 32 --adder operand widths
    width : integer := 32 --adder operand widths
  );
  );
  port (
  port (
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  );
  );
end adder_block;
end adder_block;
 
 
 
 
architecture Structural of adder_block is
architecture Structural of adder_block is
  -- array for the carry bits
  -- vector for the carry bits
  signal carry : std_logic_vector(width downto 0);
  signal carry : std_logic_vector(width downto 0);
begin
begin
  -- carry in
  -- carry in
  carry(0) <= cin;
  carry(0) <= cin;
 
 

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