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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [autorun_cntrl.vhd] - Diff between revs 2 and 3

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------------------------------------------------------------------------------------ 
----------------------------------------------------------------------  
--                      
----  autorun_ctrl                                                ---- 
-- Geoffrey Ottoy - DraMCo research group
----                                                              ---- 
--
----  This file is part of the                                    ----
-- Module Name: autorun_cntrl.vhd / entity autorun_cntrl
----    Modular Simultaneous Exponentiation Core project          ---- 
-- 
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
-- Last Modified:       25/04/2012 
----                                                              ---- 
-- 
----  Description                                                 ---- 
-- Description:         autorun control unit for a pipelined montgomery multiplier
----     autorun control unit for a pipelined montgomery          ----
--
----     multiplier                                               ----
--
----                                                              ----
-- Dependencies:        none
----  Dependencies: none                                          ----
--
----                                                              ----
-- Revision 2.00 - Major bug fix: bit_counter should count from 15 downto 0.
----  Authors:                                                    ----
-- Revision 1.00 - Architecture created
----      - Geoffrey Ottoy, DraMCo research group                 ----
-- Revision 0.01 - File Created
----      - Jonas De Craene, JonasDC@opencores.org                ---- 
-- Additional Comments: 
----                                                              ---- 
--
---------------------------------------------------------------------- 
--
----                                                              ---- 
------------------------------------------------------------------------------------
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
--
----                                                              ---- 
-- NOTICE:
---- This source file may be used and distributed without         ---- 
--
---- restriction provided that this copyright statement is not    ---- 
-- Copyright DraMCo research group. 2011. This code may be contain portions patented
---- removed from the file and that any derivative work contains  ---- 
-- by other third parties!
---- the original copyright notice and the associated disclaimer. ---- 
--
----                                                              ---- 
----------------------------------------------------------------------------------
---- This source file is free software; you can redistribute it   ---- 
library IEEE;
---- and/or modify it under the terms of the GNU Lesser General   ---- 
use IEEE.STD_LOGIC_1164.ALL;
---- Public License as published by the Free Software Foundation; ---- 
use IEEE.STD_LOGIC_ARITH.ALL;
---- either version 2.1 of the License, or (at your option) any   ---- 
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- later version.                                               ---- 
 
----                                                              ---- 
---- Uncomment the following library declaration if instantiating
---- This source is distributed in the hope that it will be       ---- 
---- any Xilinx primitives in this code.
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
--library UNISIM;
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
--use UNISIM.VComponents.all;
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
 
---- details.                                                     ---- 
 
----                                                              ---- 
 
---- You should have received a copy of the GNU Lesser General    ---- 
 
---- Public License along with this source; if not, download it   ---- 
 
---- from http://www.opencores.org/lgpl.shtml                     ---- 
 
----                                                              ---- 
 
----------------------------------------------------------------------
 
 
 
library ieee;
 
use ieee.std_logic_1164.all;
 
use ieee.std_logic_arith.all;
 
use ieee.std_logic_unsigned.all;
 
 
 
 
entity autorun_cntrl is
entity autorun_cntrl is
    Port ( clk : in  STD_LOGIC;
  port (
           reset : in  STD_LOGIC;
    clk              : in  std_logic;
           start : in  STD_LOGIC;
    reset            : in  std_logic;
           done : out  STD_LOGIC;
    start            : in  std_logic;
           op_sel : out  STD_LOGIC_VECTOR (1 downto 0);
    done             : out  std_logic;
           start_multiplier : out  STD_LOGIC;
    op_sel           : out  std_logic_vector (1 downto 0);
           multiplier_done : in  STD_LOGIC;
    start_multiplier : out  std_logic;
           read_buffer : out  STD_LOGIC;
    multiplier_done  : in  std_logic;
           buffer_din : in  STD_LOGIC_VECTOR (31 downto 0);
    read_buffer      : out  std_logic;
           buffer_empty : in  STD_LOGIC);
    buffer_din       : in  std_logic_vector (31 downto 0);
 
    buffer_empty     : in  std_logic
 
  );
end autorun_cntrl;
end autorun_cntrl;
 
 
 
 
architecture Behavioral of autorun_cntrl is
architecture Behavioral of autorun_cntrl is
 
 
        signal bit_counter_i : integer range 0 to 15 := 0;
        signal bit_counter_i : integer range 0 to 15 := 0;
        signal bit_counter_0_i : std_logic;
        signal bit_counter_0_i : std_logic;
        signal bit_counter_15_i : std_logic;
        signal bit_counter_15_i : std_logic;
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        signal e_bits_0_i : std_logic;
        signal e_bits_0_i : std_logic;
        signal cycle_counter_i : std_logic;
        signal cycle_counter_i : std_logic;
        signal op_sel_sel_i : std_logic;
        signal op_sel_sel_i : std_logic;
        signal op_sel_i : std_logic_vector(1 downto 0);
        signal op_sel_i : std_logic_vector(1 downto 0);
begin
begin
        --done <= (multiplier_done and (not running_i)) or (start and buffer_empty);
 
        done <= done_i;
        done <= done_i;
 
 
        -- the two exponents
        -- the two exponents
        e0_i <= buffer_din(15 downto 0);
        e0_i <= buffer_din(15 downto 0);
        e1_i <= buffer_din(31 downto 16);
        e1_i <= buffer_din(31 downto 16);

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