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---- Modular Simultaneous Exponentiation Core project ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- ----
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---- ----
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---- Description ----
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---- Description ----
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---- This file contains the implementation of a 1-bit full ----
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---- This file contains the implementation of a 1-bit full ----
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---- adder cell using logic gates ----
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---- adder cell using combinatorial logic ----
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---- used in adder_block ----
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---- used in adder_block ----
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---- ----
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---- ----
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---- Dependencies: none ----
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---- Dependencies: none ----
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---- ----
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---- ----
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---- Authors: ----
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---- Authors: ----
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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-- 1-bit full adder cell
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-- for use in the montgommery multiplier systolic array cells
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entity cell_1b_adder is
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entity cell_1b_adder is
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port (
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port (
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a : in std_logic;
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a : in std_logic; -- adder input operand a
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mux_result : in std_logic;
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mux_result : in std_logic; -- adder input muxed result
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cin : in std_logic;
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cin : in std_logic; -- carry in
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cout : out std_logic;
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cout : out std_logic; -- carry out
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r : out std_logic
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r : out std_logic -- result out
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);
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);
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end cell_1b_adder;
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end cell_1b_adder;
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architecture Behavioral of cell_1b_adder is
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architecture Behavioral of cell_1b_adder is
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signal a_xor_mux_result : std_logic;
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signal a_xor_mux_result : std_logic;
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begin
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begin
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-- 1-bit full adder with combinatorial logic
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-- uses 2 XOR's, 2 AND's and 1 OR port
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a_xor_mux_result <= a xor mux_result;
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a_xor_mux_result <= a xor mux_result;
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r <= a_xor_mux_result xor cin;
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r <= a_xor_mux_result xor cin;
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cout <= (a and mux_result) or (cin and a_xor_mux_result);
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cout <= (a and mux_result) or (cin and a_xor_mux_result);
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end Behavioral;
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end Behavioral;
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No newline at end of file
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No newline at end of file
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